diff mbox series

[v3,2/9] drm/i915/pps: add bxt_ prefix to pps_reset

Message ID 7d4552f555936be44fae27ca101007746fcff8c2.1726681620.git.jani.nikula@intel.com (mailing list archive)
State New, archived
Headers show
Series drm/i915/pps: hide VLV/CHV PPS pipe stuff inside intel_pps.c | expand

Commit Message

Jani Nikula Sept. 18, 2024, 5:47 p.m. UTC 
The pps_reset member of struct intel_pps is only relevant on
BXT/GLK. Prefix it with bxt_.

Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
 drivers/gpu/drm/i915/display/intel_display_types.h | 2 +-
 drivers/gpu/drm/i915/display/intel_pps.c           | 6 +++---
 2 files changed, 4 insertions(+), 4 deletions(-)
diff mbox series

Patch

diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
index d6616408df86..3e694c1204db 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -1557,7 +1557,7 @@  struct intel_pps {
 	 * Set if the sequencer may be reset due to a power transition,
 	 * requiring a reinitialization. Only relevant on BXT+.
 	 */
-	bool pps_reset;
+	bool bxt_pps_reset;
 	struct edp_power_seq pps_delays;
 	struct edp_power_seq bios_pps_delays;
 };
diff --git a/drivers/gpu/drm/i915/display/intel_pps.c b/drivers/gpu/drm/i915/display/intel_pps.c
index b7c73842ea16..2d8d911988ab 100644
--- a/drivers/gpu/drm/i915/display/intel_pps.c
+++ b/drivers/gpu/drm/i915/display/intel_pps.c
@@ -262,10 +262,10 @@  bxt_power_sequencer_idx(struct intel_dp *intel_dp)
 	/* We should never land here with regular DP ports */
 	drm_WARN_ON(display->drm, !intel_dp_is_edp(intel_dp));
 
-	if (!intel_dp->pps.pps_reset)
+	if (!intel_dp->pps.bxt_pps_reset)
 		return pps_idx;
 
-	intel_dp->pps.pps_reset = false;
+	intel_dp->pps.bxt_pps_reset = false;
 
 	/*
 	 * Only the HW needs to be reprogrammed, the SW state is fixed and
@@ -479,7 +479,7 @@  void intel_pps_reset_all(struct intel_display *display)
 			continue;
 
 		if (DISPLAY_VER(display) >= 9)
-			intel_dp->pps.pps_reset = true;
+			intel_dp->pps.bxt_pps_reset = true;
 		else
 			intel_dp->pps.vlv_pps_pipe = INVALID_PIPE;
 	}