| Message ID | 7ea79208a81fd5c3b021bcd8e1f9f90607716d82.1717514638.git.jani.nikula@intel.com (mailing list archive) |
|---|---|
| State | New |
| Headers | show |
| Series | drm/i915: finish the job of removing implicit dev_priv | expand |
On Tue, Jun 04, 2024 at 06:25:30PM +0300, Jani Nikula wrote: > Avoid the implicit dev_priv local variable use, and pass dev_priv > explicitly to the TRANS_MULT register macro. Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com> > > Signed-off-by: Jani Nikula <jani.nikula@intel.com> > --- > drivers/gpu/drm/i915/display/intel_display.c | 4 ++-- > drivers/gpu/drm/i915/i915_reg.h | 2 +- > drivers/gpu/drm/i915/intel_gvt_mmio_table.c | 6 +++--- > 3 files changed, 6 insertions(+), 6 deletions(-) > > diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c > index 81ae72648e8e..e7ee4970e306 100644 > --- a/drivers/gpu/drm/i915/display/intel_display.c > +++ b/drivers/gpu/drm/i915/display/intel_display.c > @@ -1646,7 +1646,7 @@ static void hsw_configure_cpu_transcoder(const struct intel_crtc_state *crtc_sta > intel_vrr_set_transcoder_timings(crtc_state); > > if (cpu_transcoder != TRANSCODER_EDP) > - intel_de_write(dev_priv, TRANS_MULT(cpu_transcoder), > + intel_de_write(dev_priv, TRANS_MULT(dev_priv, cpu_transcoder), > crtc_state->pixel_multiplier - 1); > > hsw_set_frame_start_delay(crtc_state); > @@ -3861,7 +3861,7 @@ static bool hsw_get_pipe_config(struct intel_crtc *crtc, > !transcoder_is_dsi(pipe_config->cpu_transcoder)) { > pipe_config->pixel_multiplier = > intel_de_read(dev_priv, > - TRANS_MULT(pipe_config->cpu_transcoder)) + 1; > + TRANS_MULT(dev_priv, pipe_config->cpu_transcoder)) + 1; > } else { > pipe_config->pixel_multiplier = 1; > } > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h > index 2e26464672f7..3bb895d030ab 100644 > --- a/drivers/gpu/drm/i915/i915_reg.h > +++ b/drivers/gpu/drm/i915/i915_reg.h > @@ -1226,7 +1226,7 @@ > #define BCLRPAT(dev_priv, trans) _MMIO_TRANS2(dev_priv, (trans), _BCLRPAT_A) > #define TRANS_VSYNCSHIFT(dev_priv, trans) _MMIO_TRANS2(dev_priv, (trans), _TRANS_VSYNCSHIFT_A) > #define PIPESRC(dev_priv, pipe) _MMIO_TRANS2(dev_priv, (pipe), _PIPEASRC) > -#define TRANS_MULT(trans) _MMIO_TRANS2(dev_priv, (trans), _TRANS_MULT_A) > +#define TRANS_MULT(dev_priv, trans) _MMIO_TRANS2(dev_priv, (trans), _TRANS_MULT_A) > > /* VRR registers */ > #define _TRANS_VRR_CTL_A 0x60420 > diff --git a/drivers/gpu/drm/i915/intel_gvt_mmio_table.c b/drivers/gpu/drm/i915/intel_gvt_mmio_table.c > index ff561a1e0fd3..600e89148f77 100644 > --- a/drivers/gpu/drm/i915/intel_gvt_mmio_table.c > +++ b/drivers/gpu/drm/i915/intel_gvt_mmio_table.c > @@ -506,9 +506,9 @@ static int iterate_generic_mmio(struct intel_gvt_mmio_table_iter *iter) > MMIO_D(GAMMA_MODE(PIPE_A)); > MMIO_D(GAMMA_MODE(PIPE_B)); > MMIO_D(GAMMA_MODE(PIPE_C)); > - MMIO_D(TRANS_MULT(TRANSCODER_A)); > - MMIO_D(TRANS_MULT(TRANSCODER_B)); > - MMIO_D(TRANS_MULT(TRANSCODER_C)); > + MMIO_D(TRANS_MULT(dev_priv, TRANSCODER_A)); > + MMIO_D(TRANS_MULT(dev_priv, TRANSCODER_B)); > + MMIO_D(TRANS_MULT(dev_priv, TRANSCODER_C)); > MMIO_D(HSW_TVIDEO_DIP_CTL(dev_priv, TRANSCODER_A)); > MMIO_D(HSW_TVIDEO_DIP_CTL(dev_priv, TRANSCODER_B)); > MMIO_D(HSW_TVIDEO_DIP_CTL(dev_priv, TRANSCODER_C)); > -- > 2.39.2 >
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c index 81ae72648e8e..e7ee4970e306 100644 --- a/drivers/gpu/drm/i915/display/intel_display.c +++ b/drivers/gpu/drm/i915/display/intel_display.c @@ -1646,7 +1646,7 @@ static void hsw_configure_cpu_transcoder(const struct intel_crtc_state *crtc_sta intel_vrr_set_transcoder_timings(crtc_state); if (cpu_transcoder != TRANSCODER_EDP) - intel_de_write(dev_priv, TRANS_MULT(cpu_transcoder), + intel_de_write(dev_priv, TRANS_MULT(dev_priv, cpu_transcoder), crtc_state->pixel_multiplier - 1); hsw_set_frame_start_delay(crtc_state); @@ -3861,7 +3861,7 @@ static bool hsw_get_pipe_config(struct intel_crtc *crtc, !transcoder_is_dsi(pipe_config->cpu_transcoder)) { pipe_config->pixel_multiplier = intel_de_read(dev_priv, - TRANS_MULT(pipe_config->cpu_transcoder)) + 1; + TRANS_MULT(dev_priv, pipe_config->cpu_transcoder)) + 1; } else { pipe_config->pixel_multiplier = 1; } diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 2e26464672f7..3bb895d030ab 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -1226,7 +1226,7 @@ #define BCLRPAT(dev_priv, trans) _MMIO_TRANS2(dev_priv, (trans), _BCLRPAT_A) #define TRANS_VSYNCSHIFT(dev_priv, trans) _MMIO_TRANS2(dev_priv, (trans), _TRANS_VSYNCSHIFT_A) #define PIPESRC(dev_priv, pipe) _MMIO_TRANS2(dev_priv, (pipe), _PIPEASRC) -#define TRANS_MULT(trans) _MMIO_TRANS2(dev_priv, (trans), _TRANS_MULT_A) +#define TRANS_MULT(dev_priv, trans) _MMIO_TRANS2(dev_priv, (trans), _TRANS_MULT_A) /* VRR registers */ #define _TRANS_VRR_CTL_A 0x60420 diff --git a/drivers/gpu/drm/i915/intel_gvt_mmio_table.c b/drivers/gpu/drm/i915/intel_gvt_mmio_table.c index ff561a1e0fd3..600e89148f77 100644 --- a/drivers/gpu/drm/i915/intel_gvt_mmio_table.c +++ b/drivers/gpu/drm/i915/intel_gvt_mmio_table.c @@ -506,9 +506,9 @@ static int iterate_generic_mmio(struct intel_gvt_mmio_table_iter *iter) MMIO_D(GAMMA_MODE(PIPE_A)); MMIO_D(GAMMA_MODE(PIPE_B)); MMIO_D(GAMMA_MODE(PIPE_C)); - MMIO_D(TRANS_MULT(TRANSCODER_A)); - MMIO_D(TRANS_MULT(TRANSCODER_B)); - MMIO_D(TRANS_MULT(TRANSCODER_C)); + MMIO_D(TRANS_MULT(dev_priv, TRANSCODER_A)); + MMIO_D(TRANS_MULT(dev_priv, TRANSCODER_B)); + MMIO_D(TRANS_MULT(dev_priv, TRANSCODER_C)); MMIO_D(HSW_TVIDEO_DIP_CTL(dev_priv, TRANSCODER_A)); MMIO_D(HSW_TVIDEO_DIP_CTL(dev_priv, TRANSCODER_B)); MMIO_D(HSW_TVIDEO_DIP_CTL(dev_priv, TRANSCODER_C));
Avoid the implicit dev_priv local variable use, and pass dev_priv explicitly to the TRANS_MULT register macro. Signed-off-by: Jani Nikula <jani.nikula@intel.com> --- drivers/gpu/drm/i915/display/intel_display.c | 4 ++-- drivers/gpu/drm/i915/i915_reg.h | 2 +- drivers/gpu/drm/i915/intel_gvt_mmio_table.c | 6 +++--- 3 files changed, 6 insertions(+), 6 deletions(-)