| Message ID | 80abf659262f193829e840db3c4d172731f08e33.1736332802.git.jani.nikula@intel.com (mailing list archive) |
|---|---|
| State | New |
| Headers | show |
| Series | drm/i915: display reset cleanups | expand |
On Wed, Jan 08, 2025 at 12:41:20PM +0200, Jani Nikula wrote: > Arguably it's a display property whether it's impacted by GPU reset. And > we don't have to look at i915 device info from display. I think everything was so mixed together back on those early platforms that it's hard to really separate GT vs display in certain cases like this. As I mentioned on the first patch, I considered it more of a GT trait (which we might be able to remove awareness of from the display code completely), but this approach is fine too. If we're moving this flag, I wonder if we should also rename the field from "gpu" to "gt" to help distinguish that we're truly talking about resets initiated through the GT's GDRST register rather than other types of resets like FLR? Matt > > Reverse the flag usage for gen 4. Only set it for the affected > platforms, instead of all gen 4 and disabling for the unaffected. > > Signed-off-by: Jani Nikula <jani.nikula@intel.com> > --- > drivers/gpu/drm/i915/display/intel_display_device.c | 5 +++++ > drivers/gpu/drm/i915/display/intel_display_device.h | 1 + > drivers/gpu/drm/i915/display/intel_display_reset.c | 4 +--- > drivers/gpu/drm/i915/i915_pci.c | 6 ------ > drivers/gpu/drm/i915/intel_device_info.h | 1 - > 5 files changed, 7 insertions(+), 10 deletions(-) > > diff --git a/drivers/gpu/drm/i915/display/intel_display_device.c b/drivers/gpu/drm/i915/display/intel_display_device.c > index 68cb7f9b9ef3..365120f3c7e1 100644 > --- a/drivers/gpu/drm/i915/display/intel_display_device.c > +++ b/drivers/gpu/drm/i915/display/intel_display_device.c > @@ -226,6 +226,7 @@ static const struct intel_display_device_info no_display = {}; > } > > #define I830_DISPLAY \ > + .gpu_reset_clobbers_display = 1, \ > .has_overlay = 1, \ > .cursor_needs_physical = 1, \ > .overlay_needs_physical = 1, \ > @@ -240,6 +241,7 @@ static const struct intel_display_device_info no_display = {}; > BIT(TRANSCODER_A) | BIT(TRANSCODER_B) > > #define I845_DISPLAY \ > + .gpu_reset_clobbers_display = 1, \ > .has_overlay = 1, \ > .overlay_needs_physical = 1, \ > .has_gmch = 1, \ > @@ -292,6 +294,7 @@ static const struct platform_desc i865g_desc = { > }; > > #define GEN3_DISPLAY \ > + .gpu_reset_clobbers_display = 1, \ > .has_gmch = 1, \ > .has_overlay = 1, \ > I9XX_PIPE_OFFSETS, \ > @@ -395,6 +398,7 @@ static const struct platform_desc i965g_desc = { > PLATFORM(i965g), > .info = &(const struct intel_display_device_info) { > GEN4_DISPLAY, > + .gpu_reset_clobbers_display = 1, > .has_overlay = 1, > > .__runtime_defaults.port_mask = BIT(PORT_B) | BIT(PORT_C), /* SDVO B/C */ > @@ -406,6 +410,7 @@ static const struct platform_desc i965gm_desc = { > PLATFORM_GROUP(mobile), > .info = &(const struct intel_display_device_info) { > GEN4_DISPLAY, > + .gpu_reset_clobbers_display = 1, > .has_overlay = 1, > .supports_tv = 1, > > diff --git a/drivers/gpu/drm/i915/display/intel_display_device.h b/drivers/gpu/drm/i915/display/intel_display_device.h > index 9a333d9e6601..3876ca39b7dd 100644 > --- a/drivers/gpu/drm/i915/display/intel_display_device.h > +++ b/drivers/gpu/drm/i915/display/intel_display_device.h > @@ -124,6 +124,7 @@ struct intel_display_platforms { > #define DEV_INFO_DISPLAY_FOR_EACH_FLAG(func) \ > /* Keep in alphabetical order */ \ > func(cursor_needs_physical); \ > + func(gpu_reset_clobbers_display); \ > func(has_cdclk_crawl); \ > func(has_cdclk_squash); \ > func(has_ddi); \ > diff --git a/drivers/gpu/drm/i915/display/intel_display_reset.c b/drivers/gpu/drm/i915/display/intel_display_reset.c > index 93399ace7761..e5c1650346fe 100644 > --- a/drivers/gpu/drm/i915/display/intel_display_reset.c > +++ b/drivers/gpu/drm/i915/display/intel_display_reset.c > @@ -15,9 +15,7 @@ > > bool intel_display_gpu_reset_clobbers_display(struct intel_display *display) > { > - struct drm_i915_private *i915 = to_i915(display->drm); > - > - return INTEL_INFO(i915)->gpu_reset_clobbers_display; > + return DISPLAY_INFO(display)->gpu_reset_clobbers_display; > } > > static bool gpu_reset_clobbers_display(struct intel_display *display) > diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c > index 21006c7f615c..85b325bafafe 100644 > --- a/drivers/gpu/drm/i915/i915_pci.c > +++ b/drivers/gpu/drm/i915/i915_pci.c > @@ -80,7 +80,6 @@ __diag_ignore_all("-Woverride-init", "Allow field initialization overrides for d > #define I830_FEATURES \ > GEN(2), \ > .is_mobile = 1, \ > - .gpu_reset_clobbers_display = true, \ > .has_3d_pipeline = 1, \ > .hws_needs_physical = 1, \ > .unfenced_needs_alignment = 1, \ > @@ -96,7 +95,6 @@ __diag_ignore_all("-Woverride-init", "Allow field initialization overrides for d > #define I845_FEATURES \ > GEN(2), \ > .has_3d_pipeline = 1, \ > - .gpu_reset_clobbers_display = true, \ > .hws_needs_physical = 1, \ > .unfenced_needs_alignment = 1, \ > .platform_engine_mask = BIT(RCS0), \ > @@ -130,7 +128,6 @@ static const struct intel_device_info i865g_info = { > > #define GEN3_FEATURES \ > GEN(3), \ > - .gpu_reset_clobbers_display = true, \ > .platform_engine_mask = BIT(RCS0), \ > .has_3d_pipeline = 1, \ > .has_snoop = true, \ > @@ -193,7 +190,6 @@ static const struct intel_device_info pnv_m_info = { > > #define GEN4_FEATURES \ > GEN(4), \ > - .gpu_reset_clobbers_display = true, \ > .platform_engine_mask = BIT(RCS0), \ > .has_3d_pipeline = 1, \ > .has_snoop = true, \ > @@ -223,7 +219,6 @@ static const struct intel_device_info g45_info = { > GEN4_FEATURES, > PLATFORM(INTEL_G45), > .platform_engine_mask = BIT(RCS0) | BIT(VCS0), > - .gpu_reset_clobbers_display = false, > }; > > static const struct intel_device_info gm45_info = { > @@ -231,7 +226,6 @@ static const struct intel_device_info gm45_info = { > PLATFORM(INTEL_GM45), > .is_mobile = 1, > .platform_engine_mask = BIT(RCS0) | BIT(VCS0), > - .gpu_reset_clobbers_display = false, > }; > > #define GEN5_FEATURES \ > diff --git a/drivers/gpu/drm/i915/intel_device_info.h b/drivers/gpu/drm/i915/intel_device_info.h > index 9387385cb418..7296e7dcf828 100644 > --- a/drivers/gpu/drm/i915/intel_device_info.h > +++ b/drivers/gpu/drm/i915/intel_device_info.h > @@ -148,7 +148,6 @@ enum intel_ppgtt_type { > /* Keep has_* in alphabetical order */ \ > func(has_64bit_reloc); \ > func(has_64k_pages); \ > - func(gpu_reset_clobbers_display); \ > func(has_reset_engine); \ > func(has_3d_pipeline); \ > func(has_flat_ccs); \ > -- > 2.39.5 >
diff --git a/drivers/gpu/drm/i915/display/intel_display_device.c b/drivers/gpu/drm/i915/display/intel_display_device.c index 68cb7f9b9ef3..365120f3c7e1 100644 --- a/drivers/gpu/drm/i915/display/intel_display_device.c +++ b/drivers/gpu/drm/i915/display/intel_display_device.c @@ -226,6 +226,7 @@ static const struct intel_display_device_info no_display = {}; } #define I830_DISPLAY \ + .gpu_reset_clobbers_display = 1, \ .has_overlay = 1, \ .cursor_needs_physical = 1, \ .overlay_needs_physical = 1, \ @@ -240,6 +241,7 @@ static const struct intel_display_device_info no_display = {}; BIT(TRANSCODER_A) | BIT(TRANSCODER_B) #define I845_DISPLAY \ + .gpu_reset_clobbers_display = 1, \ .has_overlay = 1, \ .overlay_needs_physical = 1, \ .has_gmch = 1, \ @@ -292,6 +294,7 @@ static const struct platform_desc i865g_desc = { }; #define GEN3_DISPLAY \ + .gpu_reset_clobbers_display = 1, \ .has_gmch = 1, \ .has_overlay = 1, \ I9XX_PIPE_OFFSETS, \ @@ -395,6 +398,7 @@ static const struct platform_desc i965g_desc = { PLATFORM(i965g), .info = &(const struct intel_display_device_info) { GEN4_DISPLAY, + .gpu_reset_clobbers_display = 1, .has_overlay = 1, .__runtime_defaults.port_mask = BIT(PORT_B) | BIT(PORT_C), /* SDVO B/C */ @@ -406,6 +410,7 @@ static const struct platform_desc i965gm_desc = { PLATFORM_GROUP(mobile), .info = &(const struct intel_display_device_info) { GEN4_DISPLAY, + .gpu_reset_clobbers_display = 1, .has_overlay = 1, .supports_tv = 1, diff --git a/drivers/gpu/drm/i915/display/intel_display_device.h b/drivers/gpu/drm/i915/display/intel_display_device.h index 9a333d9e6601..3876ca39b7dd 100644 --- a/drivers/gpu/drm/i915/display/intel_display_device.h +++ b/drivers/gpu/drm/i915/display/intel_display_device.h @@ -124,6 +124,7 @@ struct intel_display_platforms { #define DEV_INFO_DISPLAY_FOR_EACH_FLAG(func) \ /* Keep in alphabetical order */ \ func(cursor_needs_physical); \ + func(gpu_reset_clobbers_display); \ func(has_cdclk_crawl); \ func(has_cdclk_squash); \ func(has_ddi); \ diff --git a/drivers/gpu/drm/i915/display/intel_display_reset.c b/drivers/gpu/drm/i915/display/intel_display_reset.c index 93399ace7761..e5c1650346fe 100644 --- a/drivers/gpu/drm/i915/display/intel_display_reset.c +++ b/drivers/gpu/drm/i915/display/intel_display_reset.c @@ -15,9 +15,7 @@ bool intel_display_gpu_reset_clobbers_display(struct intel_display *display) { - struct drm_i915_private *i915 = to_i915(display->drm); - - return INTEL_INFO(i915)->gpu_reset_clobbers_display; + return DISPLAY_INFO(display)->gpu_reset_clobbers_display; } static bool gpu_reset_clobbers_display(struct intel_display *display) diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c index 21006c7f615c..85b325bafafe 100644 --- a/drivers/gpu/drm/i915/i915_pci.c +++ b/drivers/gpu/drm/i915/i915_pci.c @@ -80,7 +80,6 @@ __diag_ignore_all("-Woverride-init", "Allow field initialization overrides for d #define I830_FEATURES \ GEN(2), \ .is_mobile = 1, \ - .gpu_reset_clobbers_display = true, \ .has_3d_pipeline = 1, \ .hws_needs_physical = 1, \ .unfenced_needs_alignment = 1, \ @@ -96,7 +95,6 @@ __diag_ignore_all("-Woverride-init", "Allow field initialization overrides for d #define I845_FEATURES \ GEN(2), \ .has_3d_pipeline = 1, \ - .gpu_reset_clobbers_display = true, \ .hws_needs_physical = 1, \ .unfenced_needs_alignment = 1, \ .platform_engine_mask = BIT(RCS0), \ @@ -130,7 +128,6 @@ static const struct intel_device_info i865g_info = { #define GEN3_FEATURES \ GEN(3), \ - .gpu_reset_clobbers_display = true, \ .platform_engine_mask = BIT(RCS0), \ .has_3d_pipeline = 1, \ .has_snoop = true, \ @@ -193,7 +190,6 @@ static const struct intel_device_info pnv_m_info = { #define GEN4_FEATURES \ GEN(4), \ - .gpu_reset_clobbers_display = true, \ .platform_engine_mask = BIT(RCS0), \ .has_3d_pipeline = 1, \ .has_snoop = true, \ @@ -223,7 +219,6 @@ static const struct intel_device_info g45_info = { GEN4_FEATURES, PLATFORM(INTEL_G45), .platform_engine_mask = BIT(RCS0) | BIT(VCS0), - .gpu_reset_clobbers_display = false, }; static const struct intel_device_info gm45_info = { @@ -231,7 +226,6 @@ static const struct intel_device_info gm45_info = { PLATFORM(INTEL_GM45), .is_mobile = 1, .platform_engine_mask = BIT(RCS0) | BIT(VCS0), - .gpu_reset_clobbers_display = false, }; #define GEN5_FEATURES \ diff --git a/drivers/gpu/drm/i915/intel_device_info.h b/drivers/gpu/drm/i915/intel_device_info.h index 9387385cb418..7296e7dcf828 100644 --- a/drivers/gpu/drm/i915/intel_device_info.h +++ b/drivers/gpu/drm/i915/intel_device_info.h @@ -148,7 +148,6 @@ enum intel_ppgtt_type { /* Keep has_* in alphabetical order */ \ func(has_64bit_reloc); \ func(has_64k_pages); \ - func(gpu_reset_clobbers_display); \ func(has_reset_engine); \ func(has_3d_pipeline); \ func(has_flat_ccs); \
Arguably it's a display property whether it's impacted by GPU reset. And we don't have to look at i915 device info from display. Reverse the flag usage for gen 4. Only set it for the affected platforms, instead of all gen 4 and disabling for the unaffected. Signed-off-by: Jani Nikula <jani.nikula@intel.com> --- drivers/gpu/drm/i915/display/intel_display_device.c | 5 +++++ drivers/gpu/drm/i915/display/intel_display_device.h | 1 + drivers/gpu/drm/i915/display/intel_display_reset.c | 4 +--- drivers/gpu/drm/i915/i915_pci.c | 6 ------ drivers/gpu/drm/i915/intel_device_info.h | 1 - 5 files changed, 7 insertions(+), 10 deletions(-)