From patchwork Fri Mar 8 13:57:19 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jani Nikula X-Patchwork-Id: 2238221 Return-Path: X-Original-To: patchwork-intel-gfx@patchwork.kernel.org Delivered-To: patchwork-process-083081@patchwork1.kernel.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) by patchwork1.kernel.org (Postfix) with ESMTP id 7132B3FCF6 for ; Fri, 8 Mar 2013 14:04:09 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 2319FE6D64 for ; Fri, 8 Mar 2013 06:04:09 -0800 (PST) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga01.intel.com (mga01.intel.com [192.55.52.88]) by gabe.freedesktop.org (Postfix) with ESMTP id 55A46E6CF8 for ; Fri, 8 Mar 2013 05:56:47 -0800 (PST) Received: from fmsmga002.fm.intel.com ([10.253.24.26]) by fmsmga101.fm.intel.com with ESMTP; 08 Mar 2013 05:56:46 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="4.84,807,1355126400"; d="scan'208";a="301796700" Received: from jnikula-mobl1.fi.intel.com (HELO localhost) ([10.237.72.185]) by fmsmga002.fm.intel.com with ESMTP; 08 Mar 2013 05:56:44 -0800 From: Jani Nikula To: Jesse Barnes , intel-gfx@lists.freedesktop.org In-Reply-To: <1362175722-9281-19-git-send-email-jbarnes@virtuousgeek.org> Organization: Intel Finland Oy - BIC 0357606-4 - Westendinkatu 7, 02160 Espoo References: <1362175722-9281-1-git-send-email-jbarnes@virtuousgeek.org> <1362175722-9281-19-git-send-email-jbarnes@virtuousgeek.org> User-Agent: Notmuch/0.15.1+22~g943ed44 (http://notmuchmail.org) Emacs/23.3.1 (x86_64-pc-linux-gnu) Date: Fri, 08 Mar 2013 15:57:19 +0200 Message-ID: <877gliuh8g.fsf@intel.com> MIME-Version: 1.0 Subject: Re: [Intel-gfx] [PATCH 19/26] drm/i915: DSPFW and BLC regs are in the display offset range X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.13 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: intel-gfx-bounces+patchwork-intel-gfx=patchwork.kernel.org@lists.freedesktop.org Errors-To: intel-gfx-bounces+patchwork-intel-gfx=patchwork.kernel.org@lists.freedesktop.org I also had this as a quick fix to the backlight access; it's also incomplete wrt the backlight registers. On Sat, 02 Mar 2013, Jesse Barnes wrote: > Signed-off-by: Jesse Barnes > --- > drivers/gpu/drm/i915/i915_reg.h | 8 +++++--- > 1 file changed, 5 insertions(+), 3 deletions(-) > > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h > index 558c6d1..c70e6d3 100644 > --- a/drivers/gpu/drm/i915/i915_reg.h > +++ b/drivers/gpu/drm/i915/i915_reg.h > @@ -1953,7 +1953,7 @@ > #define PFIT_AUTO_RATIOS (dev_priv->info->display_mmio_offset + 0x61238) > > /* Backlight control */ > -#define BLC_PWM_CTL2 0x61250 /* 965+ only */ > +#define BLC_PWM_CTL2 (dev_priv->info->display_mmio_offset + 0x61250) /* 965+ only */ > #define BLM_PWM_ENABLE (1 << 31) > #define BLM_COMBINATION_MODE (1 << 30) /* gen4 only */ > #define BLM_PIPE_SELECT (1 << 29) > @@ -1972,7 +1972,7 @@ > #define BLM_PHASE_IN_COUNT_MASK (0xff << 8) > #define BLM_PHASE_IN_INCR_SHIFT (0) > #define BLM_PHASE_IN_INCR_MASK (0xff << 0) > -#define BLC_PWM_CTL 0x61254 > +#define BLC_PWM_CTL (dev_priv->info->display_mmio_offset + 0x61254) > /* > * This is the most significant 15 bits of the number of backlight cycles in a > * complete cycle of the modulated backlight control. > @@ -1994,7 +1994,7 @@ > #define BACKLIGHT_DUTY_CYCLE_MASK_PNV (0xfffe) > #define BLM_POLARITY_PNV (1 << 0) /* pnv only */ > > -#define BLC_HIST_CTL 0x61260 > +#define BLC_HIST_CTL (dev_priv->info->display_mmio_offset + 0x61260) > > /* New registers for PCH-split platforms. Safe where new bits show up, the > * register layout machtes with gen4 BLC_PWM_CTL[12]. */ > @@ -2831,6 +2831,8 @@ > #define DSPFW_HPLL_CURSOR_SHIFT 16 > #define DSPFW_HPLL_CURSOR_MASK (0x3f<<16) > #define DSPFW_HPLL_SR_MASK (0x1ff) > +#define DSPFW4 (dev_priv->info->display_mmio_offset + 0x70070) > +#define DSPFW7 (dev_priv->info->display_mmio_offset + 0x7007c) > > /* drain latency register values*/ > #define DRAIN_LATENCY_PRECISION_32 32 > -- > 1.7.9.5 > > _______________________________________________ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > http://lists.freedesktop.org/mailman/listinfo/intel-gfx --- a/drivers/gpu/drm/i915/intel_panel.c +++ b/drivers/gpu/drm/i915/intel_panel.c @@ -121,6 +121,9 @@ static int is_backlight_combination_mode(struct drm_device *dev) { struct drm_i915_private *dev_priv = dev->dev_private; + if (IS_VALLEYVIEW(dev)) + return 0; + if (INTEL_INFO(dev)->gen >= 4) return I915_READ(BLC_PWM_CTL2) & BLM_COMBINATION_MODE; @@ -338,12 +341,15 @@ void intel_panel_enable_backlight(struct drm_device *dev, if (tmp & BLM_PWM_ENABLE) goto set_level; - if (dev_priv->num_pipe == 3) - tmp &= ~BLM_PIPE_SELECT_IVB; - else - tmp &= ~BLM_PIPE_SELECT; + /* XXX: VLV per pipe registers */ + if (!IS_VALLEYVIEW(dev)) { + if (dev_priv->num_pipe == 3) + tmp &= ~BLM_PIPE_SELECT_IVB; + else + tmp &= ~BLM_PIPE_SELECT; - tmp |= BLM_PIPE(pipe); + tmp |= BLM_PIPE(pipe); + } tmp &= ~BLM_PWM_ENABLE; I915_WRITE(reg, tmp);