diff mbox

[2/5] drm/i915: Read test values for lane_count and link_rate

Message ID 87E1A67218970041879FDD2045F7145D02A67E94@ORSMSX106.amr.corp.intel.com (mailing list archive)
State New, archived
Headers show

Commit Message

Navare, Manasi April 26, 2016, 4:09 a.m. UTC
The automated test request for link training needs to start the link training with the requested link rate and lane count. So after reading the TEST LANE COUNT and TEST LINK RATE values, it needs to call intel_dp_start_link_train() also.
How is the automated link train being tested currently? Could you add some details of the automated testing (test numbers from the CTS usite) in the commit message.

Regards,
Manasi Navare
Graphics Kernel Developer
OTC, Intel Corporation


-----Original Message-----
From: Intel-gfx [mailto:intel-gfx-bounces@lists.freedesktop.org] On Behalf Of Shubhangi Shrivastava
Sent: Monday, April 25, 2016 1:24 AM
To: intel-gfx@lists.freedesktop.org
Cc: Shrivastava, Shubhangi
Subject: [Intel-gfx] [PATCH 2/5] drm/i915: Read test values for lane_count and link_rate

During automated test request for link training we are supposed to read the TEST_LANE_COUNT and TEST_LINK_RATE dpcd registers and use respective values in the next link training. This patch adds reading and updating of these values.

Signed-off-by: Sivakumar Thulasimani <sivakumar.thulasimani@intel.com>
Signed-off-by: Shubhangi Shrivastava <shubhangi.shrivastava@intel.com>
---
 drivers/gpu/drm/i915/intel_dp.c | 25 +++++++++++++++++++++++++
 1 file changed, 25 insertions(+)


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Comments

Shubhangi Shrivastava May 2, 2016, 9:08 a.m. UTC | #1
This patch is intended to read test values only. Call to 
intel_dp_start_link_train will be in upcoming patch "Lane count change 
detection", which I will be posting after this patch series..

On Tuesday 26 April 2016 09:39 AM, Navare, Manasi D wrote:
> The automated test request for link training needs to start the link training with the requested link rate and lane count. So after reading the TEST LANE COUNT and TEST LINK RATE values, it needs to call intel_dp_start_link_train() also.
> How is the automated link train being tested currently? Could you add some details of the automated testing (test numbers from the CTS usite) in the commit message.
>
> Regards,
> Manasi Navare
> Graphics Kernel Developer
> OTC, Intel Corporation
>
>
> -----Original Message-----
> From: Intel-gfx [mailto:intel-gfx-bounces@lists.freedesktop.org] On Behalf Of Shubhangi Shrivastava
> Sent: Monday, April 25, 2016 1:24 AM
> To: intel-gfx@lists.freedesktop.org
> Cc: Shrivastava, Shubhangi
> Subject: [Intel-gfx] [PATCH 2/5] drm/i915: Read test values for lane_count and link_rate
>
> During automated test request for link training we are supposed to read the TEST_LANE_COUNT and TEST_LINK_RATE dpcd registers and use respective values in the next link training. This patch adds reading and updating of these values.
>
> Signed-off-by: Sivakumar Thulasimani <sivakumar.thulasimani@intel.com>
> Signed-off-by: Shubhangi Shrivastava <shubhangi.shrivastava@intel.com>
> ---
>   drivers/gpu/drm/i915/intel_dp.c | 25 +++++++++++++++++++++++++
>   1 file changed, 25 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c index 1b26c59..387800b 100644
> --- a/drivers/gpu/drm/i915/intel_dp.c
> +++ b/drivers/gpu/drm/i915/intel_dp.c
> @@ -4010,9 +4010,34 @@ intel_dp_get_sink_irq_esi(struct intel_dp *intel_dp, u8 *sink_irq_vector)
>   	return true;
>   }
>   
> +/*
> + * This function reads TEST_LANE_COUNT & TEST_LINK_RATE and updates
> + * them to cached dpcd values, thus the new values are implicitly
> + * used by rest of the code without need to be aware of the change.
> + */
>   static uint8_t intel_dp_autotest_link_training(struct intel_dp *intel_dp)  {
>   	uint8_t test_result = DP_TEST_ACK;
> +	uint8_t dpcd_val, ret;
> +
> +	ret = drm_dp_dpcd_read(&intel_dp->aux,
> +			       DP_TEST_LANE_COUNT,
> +			       &dpcd_val, 1);
> +
> +	/* update values only if read returned 1 byte */
> +	if (ret == 1) {
> +		dpcd_val &= DP_MAX_LANE_COUNT_MASK;
> +		intel_dp->dpcd[DP_MAX_LANE_COUNT] &= ~(DP_MAX_LANE_COUNT_MASK);
> +		intel_dp->dpcd[DP_MAX_LANE_COUNT] |= dpcd_val;
> +	}
> +
> +	ret = drm_dp_dpcd_read(&intel_dp->aux,
> +			       DP_TEST_LINK_RATE,
> +			       &dpcd_val, 1);
> +
> +	if (ret == 1)
> +		intel_dp->dpcd[DP_MAX_LINK_RATE] = dpcd_val;
> +
>   	return test_result;
>   }
>   
> --
> 2.6.1
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Sivakumar Thulasimani May 2, 2016, 9:16 a.m. UTC | #2
On 5/2/2016 2:38 PM, Shubhangi Shrivastava wrote:
> This patch is intended to read test values only. Call to 
> intel_dp_start_link_train will be in upcoming patch "Lane count change 
> detection", which I will be posting after this patch series..
>
> On Tuesday 26 April 2016 09:39 AM, Navare, Manasi D wrote:
>> The automated test request for link training needs to start the link 
>> training with the requested link rate and lane count. So after 
>> reading the TEST LANE COUNT and TEST LINK RATE values, it needs to 
>> call intel_dp_start_link_train() also.
>> How is the automated link train being tested currently? Could you add 
>> some details of the automated testing (test numbers from the CTS 
>> usite) in the commit message.
>>
>> Regards,
>> Manasi Navare
>> Graphics Kernel Developer
>> OTC, Intel Corporation
>>
>>
Almost all link training tests in CTS use the TEST LANE COUNT and TEST 
LINK RATE values.
i.e 4.3.1.1 to 4.3.1.10 and 4.3.2.1 to 4.3.2.6.
This was tested using DPR100 & DPR120 compliance test tool from Unigraf.
As mentioned by Shubhangi this is just a clean up patch and further 
patches will complete
the process of using the test values in next link training.

To give some background, if you run either of the tools mentioned above, 
they give us a
short/long pulse with TEST_LINK_TRAIN request bit set, we are supposed 
to then read the
link rate and lane count values from appropriate Test DPCD registers and 
use them
in the following link training.  So as per compliance requirements you 
need to use
these values in the next link training (which is assumed to be as part 
of modeset
if we got it as part of long pulse and for short pulse we can explicitly 
retrain the link)

regards,
Sivakumar
>> -----Original Message-----
>> From: Intel-gfx [mailto:intel-gfx-bounces@lists.freedesktop.org] On 
>> Behalf Of Shubhangi Shrivastava
>> Sent: Monday, April 25, 2016 1:24 AM
>> To: intel-gfx@lists.freedesktop.org
>> Cc: Shrivastava, Shubhangi
>> Subject: [Intel-gfx] [PATCH 2/5] drm/i915: Read test values for 
>> lane_count and link_rate
>>
>> During automated test request for link training we are supposed to 
>> read the TEST_LANE_COUNT and TEST_LINK_RATE dpcd registers and use 
>> respective values in the next link training. This patch adds reading 
>> and updating of these values.
>>
>> Signed-off-by: Sivakumar Thulasimani <sivakumar.thulasimani@intel.com>
>> Signed-off-by: Shubhangi Shrivastava <shubhangi.shrivastava@intel.com>
>> ---
>>   drivers/gpu/drm/i915/intel_dp.c | 25 +++++++++++++++++++++++++
>>   1 file changed, 25 insertions(+)
>>
>> diff --git a/drivers/gpu/drm/i915/intel_dp.c 
>> b/drivers/gpu/drm/i915/intel_dp.c index 1b26c59..387800b 100644
>> --- a/drivers/gpu/drm/i915/intel_dp.c
>> +++ b/drivers/gpu/drm/i915/intel_dp.c
>> @@ -4010,9 +4010,34 @@ intel_dp_get_sink_irq_esi(struct intel_dp 
>> *intel_dp, u8 *sink_irq_vector)
>>       return true;
>>   }
>>   +/*
>> + * This function reads TEST_LANE_COUNT & TEST_LINK_RATE and updates
>> + * them to cached dpcd values, thus the new values are implicitly
>> + * used by rest of the code without need to be aware of the change.
>> + */
>>   static uint8_t intel_dp_autotest_link_training(struct intel_dp 
>> *intel_dp)  {
>>       uint8_t test_result = DP_TEST_ACK;
>> +    uint8_t dpcd_val, ret;
>> +
>> +    ret = drm_dp_dpcd_read(&intel_dp->aux,
>> +                   DP_TEST_LANE_COUNT,
>> +                   &dpcd_val, 1);
>> +
>> +    /* update values only if read returned 1 byte */
>> +    if (ret == 1) {
>> +        dpcd_val &= DP_MAX_LANE_COUNT_MASK;
>> +        intel_dp->dpcd[DP_MAX_LANE_COUNT] &= ~(DP_MAX_LANE_COUNT_MASK);
>> +        intel_dp->dpcd[DP_MAX_LANE_COUNT] |= dpcd_val;
>> +    }
>> +
>> +    ret = drm_dp_dpcd_read(&intel_dp->aux,
>> +                   DP_TEST_LINK_RATE,
>> +                   &dpcd_val, 1);
>> +
>> +    if (ret == 1)
>> +        intel_dp->dpcd[DP_MAX_LINK_RATE] = dpcd_val;
>> +
>>       return test_result;
>>   }
>>   --
>> 2.6.1
>>
>> _______________________________________________
>> Intel-gfx mailing list
>> Intel-gfx@lists.freedesktop.org
>> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
>
diff mbox

Patch

diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c index 1b26c59..387800b 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -4010,9 +4010,34 @@  intel_dp_get_sink_irq_esi(struct intel_dp *intel_dp, u8 *sink_irq_vector)
 	return true;
 }
 
+/*
+ * This function reads TEST_LANE_COUNT & TEST_LINK_RATE and updates
+ * them to cached dpcd values, thus the new values are implicitly
+ * used by rest of the code without need to be aware of the change.
+ */
 static uint8_t intel_dp_autotest_link_training(struct intel_dp *intel_dp)  {
 	uint8_t test_result = DP_TEST_ACK;
+	uint8_t dpcd_val, ret;
+
+	ret = drm_dp_dpcd_read(&intel_dp->aux,
+			       DP_TEST_LANE_COUNT,
+			       &dpcd_val, 1);
+
+	/* update values only if read returned 1 byte */
+	if (ret == 1) {
+		dpcd_val &= DP_MAX_LANE_COUNT_MASK;
+		intel_dp->dpcd[DP_MAX_LANE_COUNT] &= ~(DP_MAX_LANE_COUNT_MASK);
+		intel_dp->dpcd[DP_MAX_LANE_COUNT] |= dpcd_val;
+	}
+
+	ret = drm_dp_dpcd_read(&intel_dp->aux,
+			       DP_TEST_LINK_RATE,
+			       &dpcd_val, 1);
+
+	if (ret == 1)
+		intel_dp->dpcd[DP_MAX_LINK_RATE] = dpcd_val;
+
 	return test_result;
 }
 
--
2.6.1