| Message ID | 87d8d80ba205eb2ecb50f613219e0a821a842616.1630419362.git.jani.nikula@intel.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | drm/displayid: VESA vendor block and drm/i915 MSO use of it | expand |
> -----Original Message----- > From: Intel-gfx <intel-gfx-bounces@lists.freedesktop.org> On Behalf Of Jani Nikula > Sent: Tuesday, August 31, 2021 7:48 PM > To: intel-gfx@lists.freedesktop.org > Cc: dri-devel@lists.freedesktop.org; ville.syrjala@linux.intel.com; Nikula, Jani > <jani.nikula@intel.com> > Subject: [Intel-gfx] [PATCH v2 6/6] drm/i915/edp: use MSO pixel overlap from > DisplayID data > > Now that we have MSO pixel overlap in display info, use it. > Looks ok to me. Reviewed-by: Uma Shankar <uma.shankar@intel.com> > Signed-off-by: Jani Nikula <jani.nikula@intel.com> > --- > drivers/gpu/drm/i915/display/intel_dp.c | 9 ++++++--- > 1 file changed, 6 insertions(+), 3 deletions(-) > > diff --git a/drivers/gpu/drm/i915/display/intel_dp.c > b/drivers/gpu/drm/i915/display/intel_dp.c > index df402f63b741..baf21f9aa40e 100644 > --- a/drivers/gpu/drm/i915/display/intel_dp.c > +++ b/drivers/gpu/drm/i915/display/intel_dp.c > @@ -2420,6 +2420,8 @@ static void intel_edp_mso_mode_fixup(struct > intel_connector *connector, static void intel_edp_mso_init(struct intel_dp > *intel_dp) { > struct drm_i915_private *i915 = dp_to_i915(intel_dp); > + struct intel_connector *connector = intel_dp->attached_connector; > + struct drm_display_info *info = &connector->base.display_info; > u8 mso; > > if (intel_dp->edp_dpcd[0] < DP_EDP_14) @@ -2438,8 +2440,9 @@ static > void intel_edp_mso_init(struct intel_dp *intel_dp) > } > > if (mso) { > - drm_dbg_kms(&i915->drm, "Sink MSO %ux%u configuration\n", > - mso, drm_dp_max_lane_count(intel_dp->dpcd) / mso); > + drm_dbg_kms(&i915->drm, "Sink MSO %ux%u configuration, pixel > overlap %u\n", > + mso, drm_dp_max_lane_count(intel_dp->dpcd) / mso, > + info->mso_pixel_overlap); > if (!HAS_MSO(i915)) { > drm_err(&i915->drm, "No source MSO support, > disabling\n"); > mso = 0; > @@ -2447,7 +2450,7 @@ static void intel_edp_mso_init(struct intel_dp *intel_dp) > } > > intel_dp->mso_link_count = mso; > - intel_dp->mso_pixel_overlap = 0; /* FIXME: read from DisplayID v2.0 */ > + intel_dp->mso_pixel_overlap = mso ? info->mso_pixel_overlap : 0; > } > > static bool > -- > 2.30.2
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c index df402f63b741..baf21f9aa40e 100644 --- a/drivers/gpu/drm/i915/display/intel_dp.c +++ b/drivers/gpu/drm/i915/display/intel_dp.c @@ -2420,6 +2420,8 @@ static void intel_edp_mso_mode_fixup(struct intel_connector *connector, static void intel_edp_mso_init(struct intel_dp *intel_dp) { struct drm_i915_private *i915 = dp_to_i915(intel_dp); + struct intel_connector *connector = intel_dp->attached_connector; + struct drm_display_info *info = &connector->base.display_info; u8 mso; if (intel_dp->edp_dpcd[0] < DP_EDP_14) @@ -2438,8 +2440,9 @@ static void intel_edp_mso_init(struct intel_dp *intel_dp) } if (mso) { - drm_dbg_kms(&i915->drm, "Sink MSO %ux%u configuration\n", - mso, drm_dp_max_lane_count(intel_dp->dpcd) / mso); + drm_dbg_kms(&i915->drm, "Sink MSO %ux%u configuration, pixel overlap %u\n", + mso, drm_dp_max_lane_count(intel_dp->dpcd) / mso, + info->mso_pixel_overlap); if (!HAS_MSO(i915)) { drm_err(&i915->drm, "No source MSO support, disabling\n"); mso = 0; @@ -2447,7 +2450,7 @@ static void intel_edp_mso_init(struct intel_dp *intel_dp) } intel_dp->mso_link_count = mso; - intel_dp->mso_pixel_overlap = 0; /* FIXME: read from DisplayID v2.0 */ + intel_dp->mso_pixel_overlap = mso ? info->mso_pixel_overlap : 0; } static bool
Now that we have MSO pixel overlap in display info, use it. Signed-off-by: Jani Nikula <jani.nikula@intel.com> --- drivers/gpu/drm/i915/display/intel_dp.c | 9 ++++++--- 1 file changed, 6 insertions(+), 3 deletions(-)