From patchwork Thu Apr 30 08:43:51 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jani Nikula X-Patchwork-Id: 6300571 Return-Path: X-Original-To: patchwork-intel-gfx@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork1.web.kernel.org (Postfix) with ESMTP id 094A99F373 for ; Thu, 30 Apr 2015 08:42:01 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 21DB0201BB for ; Thu, 30 Apr 2015 08:42:00 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) by mail.kernel.org (Postfix) with ESMTP id 9B5162013D for ; Thu, 30 Apr 2015 08:41:54 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 98CF86E29B; Thu, 30 Apr 2015 01:41:53 -0700 (PDT) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga14.intel.com (mga14.intel.com [192.55.52.115]) by gabe.freedesktop.org (Postfix) with ESMTP id 038DD6E29B for ; Thu, 30 Apr 2015 01:41:51 -0700 (PDT) Received: from fmsmga002.fm.intel.com ([10.253.24.26]) by fmsmga103.fm.intel.com with ESMTP; 30 Apr 2015 01:41:52 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.11,675,1422950400"; d="scan'208";a="718303832" Received: from jnikula-mobl.fi.intel.com (HELO localhost) ([10.237.72.152]) by fmsmga002.fm.intel.com with ESMTP; 30 Apr 2015 01:41:52 -0700 From: Jani Nikula To: Vandana Kannan , intel-gfx@lists.freedesktop.org In-Reply-To: <1430379455-21244-3-git-send-email-vandana.kannan@intel.com> Organization: Intel Finland Oy - BIC 0357606-4 - Westendinkatu 7, 02160 Espoo References: <1430379455-21244-1-git-send-email-vandana.kannan@intel.com> <1430379455-21244-3-git-send-email-vandana.kannan@intel.com> User-Agent: Notmuch/0.19+87~gcf99a78 (http://notmuchmail.org) Emacs/24.4.1 (x86_64-pc-linux-gnu) Date: Thu, 30 Apr 2015 11:43:51 +0300 Message-ID: <87twvy9faw.fsf@intel.com> MIME-Version: 1.0 Subject: Re: [Intel-gfx] [PATCH 3/3] drm/i915: eDP Panel Power sequencing add PPS reg set X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Spam-Status: No, score=-4.2 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_MED, T_RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP On Thu, 30 Apr 2015, Vandana Kannan wrote: > Second set of PPS registers have been defined but will be used when VBT > provides a selection between the 2 sets of registers. > > Signed-off-by: Vandana Kannan > Signed-off-by: A.Sunil Kamath > --- > drivers/gpu/drm/i915/i915_reg.h | 6 ++++++ > 1 file changed, 6 insertions(+) > > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h > index 580f5cb..199a1747 100644 > --- a/drivers/gpu/drm/i915/i915_reg.h > +++ b/drivers/gpu/drm/i915/i915_reg.h > @@ -6345,6 +6345,12 @@ enum skl_disp_power_wells { > #define PANEL_POWER_CYCLE_DELAY_MASK (0x1f) > #define PANEL_POWER_CYCLE_DELAY_SHIFT 0 > > +/* BXT PPS changes - 2nd set of PPS registers */ > +#define BXT_PP_STATUS2 0xc7300 > +#define BXT_PP_CONTROL2 0xc7304 > +#define BXT_PP_ON_DELAYS2 0xc7308 > +#define BXT_PP_OFF_DELAYS2 0xc730c > + > #define PCH_DP_B 0xe4100 > #define PCH_DPB_AUX_CH_CTL 0xe4110 > #define PCH_DPB_AUX_CH_DATA1 0xe4114 How about doing this patch first, with something like: And you could use BXT_PP_* from the start. I believe this will add clarity to the usage and pinpoint where you'll need to touch the code to enable the 2nd power sequencer. BR, Jani. > -- > 2.0.1 > > _______________________________________________ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > http://lists.freedesktop.org/mailman/listinfo/intel-gfx diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 435c372d001e..a3af3526cb4f 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -6343,6 +6343,17 @@ enum skl_disp_power_wells { #define PANEL_POWER_CYCLE_DELAY_MASK (0x1f) #define PANEL_POWER_CYCLE_DELAY_SHIFT 0 +/* BXT PPS changes - 2nd set of PPS registers */ +#define _BXT_PP_STATUS2 0xc7300 +#define _BXT_PP_CONTROL2 0xc7304 +#define _BXT_PP_ON_DELAYS2 0xc7308 +#define _BXT_PP_OFF_DELAYS2 0xc730c + +#define BXT_PP_STATUS(n) ((!n) ? PCH_PP_STATUS : _BXT_PP_STATUS2) +#define BXT_PP_CONTROL(n) ((!n) ? PCH_PP_CONTROL : _BXT_PP_CONTROL2) +#define BXT_PP_ON_DELAYS(n) ((!n) ? PCH_PP_ON_DELAYS : _BXT_PP_ON_DELAYS2) +#define BXT_PP_OFF_DELAYS(n) ((!n) ? PCH_PP_OFF_DELAYS : _BXT_PP_OFF_DELAYS2) + #define PCH_DP_B 0xe4100 #define PCH_DPB_AUX_CH_CTL 0xe4110 #define PCH_DPB_AUX_CH_DATA1 0xe4114