From patchwork Fri Jan 15 13:04:27 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Chris Wilson X-Patchwork-Id: 73170 Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) by demeter.kernel.org (8.14.3/8.14.2) with ESMTP id o0FD4bkF010105 for ; Fri, 15 Jan 2010 13:04:37 GMT Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 6EC639F4C0; Fri, 15 Jan 2010 05:04:37 -0800 (PST) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from orsmga101.jf.intel.com (mga06.intel.com [134.134.136.21]) by gabe.freedesktop.org (Postfix) with ESMTP id DC60C9F3BD for ; Fri, 15 Jan 2010 05:04:34 -0800 (PST) Received: from orsmga002.jf.intel.com ([10.7.209.21]) by orsmga101.jf.intel.com with ESMTP; 15 Jan 2010 05:04:14 -0800 Message-Id: <89khjo$edq401@orsmga002.jf.intel.com> X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="4.49,282,1262592000"; d="scan'208";a="484249601" Received: from unknown (HELO cwilso3-mobl.ger.corp.intel.com) ([10.255.17.133]) by orsmga002.jf.intel.com with SMTP; 15 Jan 2010 05:04:29 -0800 Received: by cwilso3-mobl.ger.corp.intel.com (sSMTP sendmail emulation); Fri, 15 Jan 2010 13:04:27 +0000 Date: Fri, 15 Jan 2010 13:04:27 +0000 To: Daniel Vetter , intel-gfx@lists.freedesktop.org References: <218f84ba918f387762e080160db19fbf90b63462.1263558064.git.daniel.vetter@ffwll.ch> From: Chris Wilson In-Reply-To: <218f84ba918f387762e080160db19fbf90b63462.1263558064.git.daniel.vetter@ffwll.ch> Cc: Daniel Vetter Subject: Re: [Intel-gfx] [PATCH 08/11] drm/i915: fixup i915_gem_evict_everything to actually evict everything X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.9 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: intel-gfx-bounces@lists.freedesktop.org Errors-To: intel-gfx-bounces@lists.freedesktop.org diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index 835625b..3481570 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -464,6 +464,15 @@ typedef struct drm_i915_private { struct list_head flushing_list; /** + * List of objects currently pending a GPU write. + * + * All elements on this list will belong to either the + * active_list or flushing_list, last_rendering_seqno can + * be used to differentiate between the two elements. + */ + struct list_head gpu_write_list; + + /** * LRU list of objects which are not in the ringbuffer and * are ready to unbind, but are still in the GTT. * @@ -554,6 +563,8 @@ struct drm_i915_gem_object { /** This object's place on the active/flushing/inactive lists */ struct list_head list; + /** This object's place on GPU write list */ + struct list_head gpu_write_list; /** This object's place on the fenced object LRU */ struct list_head fence_list; diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c index a25b878..6dd451e 100644 --- a/drivers/gpu/drm/i915/i915_gem.c +++ b/drivers/gpu/drm/i915/i915_gem.c @@ -1570,6 +1570,8 @@ i915_gem_object_move_to_inactive(struct drm_gem_object *obj) else list_move_tail(&obj_priv->list, &dev_priv->mm.inactive_list); + BUG_ON(!list_empty(&obj_priv->gpu_write_list)); + obj_priv->last_rendering_seqno = 0; if (obj_priv->active) { obj_priv->active = 0; @@ -1633,21 +1635,21 @@ i915_add_request(struct drm_device *dev, struct drm_file *file_priv, INIT_LIST_HEAD(&request->client_list); } - /* Associate any objects on the flushing list matching the write + /* Associate any objects on the gpu_write_list matching the write * domain we're flushing with our flush. */ - if (flush_domains != 0) { + if (flush_domains & I915_GEM_GPU_DOMAINS) { struct drm_i915_gem_object *obj_priv, *next; list_for_each_entry_safe(obj_priv, next, - &dev_priv->mm.flushing_list, list) { + &dev_priv->mm.gpu_write_list, + gpu_write_list) { struct drm_gem_object *obj = obj_priv->obj; - if ((obj->write_domain & flush_domains) == - obj->write_domain) { + if (obj->write_domain & flush_domains) { uint32_t old_write_domain = obj->write_domain; - obj->write_domain = 0; + list_del_init(&obj_priv->gpu_write_list); i915_gem_object_move_to_active(obj, seqno); trace_i915_gem_object_change_domain(obj, @@ -1655,7 +1657,6 @@ i915_add_request(struct drm_device *dev, struct drm_file *file_priv, old_write_domain); } } - } if (!dev_priv->mm.suspended) { @@ -2725,7 +2726,7 @@ i915_gem_object_flush_gpu_write_domain(struct drm_gem_object *obj) old_write_domain = obj->write_domain; i915_gem_flush(dev, 0, obj->write_domain); seqno = i915_add_request(dev, NULL, obj->write_domain); - obj->write_domain = 0; + BUG_ON(obj->write_domain); i915_gem_object_move_to_active(obj, seqno); trace_i915_gem_object_change_domain(obj, @@ -3745,16 +3746,23 @@ i915_gem_execbuffer(struct drm_device *dev, void *data, i915_gem_flush(dev, dev->invalidate_domains, dev->flush_domains); - if (dev->flush_domains) + if (dev->flush_domains & I915_GEM_GPU_DOMAINS) (void)i915_add_request(dev, file_priv, dev->flush_domains); } for (i = 0; i < args->buffer_count; i++) { struct drm_gem_object *obj = object_list[i]; + struct drm_i915_gem_object *obj_priv = obj->driver_private; uint32_t old_write_domain = obj->write_domain; obj->write_domain = obj->pending_write_domain; + if (obj->write_domain) + list_move_tail(&obj_priv->gpu_write_list, + &dev_priv->mm.gpu_write_list); + else + list_del_init(&obj_priv->gpu_write_list); + trace_i915_gem_object_change_domain(obj, obj->read_domains, old_write_domain); @@ -4147,6 +4155,7 @@ int i915_gem_init_object(struct drm_gem_object *obj) obj_priv->obj = obj; obj_priv->fence_reg = I915_FENCE_REG_NONE; INIT_LIST_HEAD(&obj_priv->list); + INIT_LIST_HEAD(&obj_priv->gpu_write_list); INIT_LIST_HEAD(&obj_priv->fence_list); obj_priv->madv = I915_MADV_WILLNEED; @@ -4281,14 +4290,18 @@ i915_gem_idle(struct drm_device *dev) * the GPU domains and just stuff them onto inactive. */ while (!list_empty(&dev_priv->mm.active_list)) { + struct drm_i915_gem_object *obj_priv; struct drm_gem_object *obj; uint32_t old_write_domain; - obj = list_first_entry(&dev_priv->mm.active_list, - struct drm_i915_gem_object, - list)->obj; + obj_priv = list_first_entry(&dev_priv->mm.active_list, + struct drm_i915_gem_object, + list); + obj = obj_priv->obj; old_write_domain = obj->write_domain; obj->write_domain &= ~I915_GEM_GPU_DOMAINS; + if (!list_empty(&obj_priv->gpu_write_list)) + list_del_init (&obj_priv->gpu_write_list); i915_gem_object_move_to_inactive(obj); trace_i915_gem_object_change_domain(obj, @@ -4298,14 +4311,18 @@ i915_gem_idle(struct drm_device *dev) spin_unlock(&dev_priv->mm.active_list_lock); while (!list_empty(&dev_priv->mm.flushing_list)) { + struct drm_i915_gem_object *obj_priv; struct drm_gem_object *obj; uint32_t old_write_domain; - obj = list_first_entry(&dev_priv->mm.flushing_list, - struct drm_i915_gem_object, - list)->obj; + obj_priv = list_first_entry(&dev_priv->mm.flushing_list, + struct drm_i915_gem_object, + list); + obj = obj_priv->obj; old_write_domain = obj->write_domain; obj->write_domain &= ~I915_GEM_GPU_DOMAINS; + if (!list_empty(&obj_priv->gpu_write_list)) + list_del_init (&obj_priv->gpu_write_list); i915_gem_object_move_to_inactive(obj); trace_i915_gem_object_change_domain(obj, @@ -4598,6 +4615,7 @@ i915_gem_load(struct drm_device *dev) spin_lock_init(&dev_priv->mm.active_list_lock); INIT_LIST_HEAD(&dev_priv->mm.active_list); INIT_LIST_HEAD(&dev_priv->mm.flushing_list); + INIT_LIST_HEAD(&dev_priv->mm.gpu_write_list); INIT_LIST_HEAD(&dev_priv->mm.inactive_list); INIT_LIST_HEAD(&dev_priv->mm.request_list); INIT_LIST_HEAD(&dev_priv->mm.fence_list);