From patchwork Thu Apr 24 09:44:28 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: akash.goel@intel.com X-Patchwork-Id: 4047111 Return-Path: X-Original-To: patchwork-intel-gfx@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork2.web.kernel.org (Postfix) with ESMTP id A9CA4BFF02 for ; Thu, 24 Apr 2014 09:44:38 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id D10C9201BB for ; Thu, 24 Apr 2014 09:44:37 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) by mail.kernel.org (Postfix) with ESMTP id D710B2018E for ; Thu, 24 Apr 2014 09:44:36 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 372076E034; Thu, 24 Apr 2014 02:44:36 -0700 (PDT) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga02.intel.com (mga02.intel.com [134.134.136.20]) by gabe.freedesktop.org (Postfix) with ESMTP id B36546E034 for ; Thu, 24 Apr 2014 02:44:34 -0700 (PDT) Received: from orsmga002.jf.intel.com ([10.7.209.21]) by orsmga101.jf.intel.com with ESMTP; 24 Apr 2014 02:44:34 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="4.97,917,1389772800"; d="scan'208";a="527160574" Received: from fmsmsx108.amr.corp.intel.com ([10.19.9.228]) by orsmga002.jf.intel.com with ESMTP; 24 Apr 2014 02:44:33 -0700 Received: from fmsmsx101.amr.corp.intel.com (10.19.9.52) by FMSMSX108.amr.corp.intel.com (10.19.9.228) with Microsoft SMTP Server (TLS) id 14.3.123.3; Thu, 24 Apr 2014 02:44:32 -0700 Received: from bgsmsx102.gar.corp.intel.com (10.223.4.172) by FMSMSX101.amr.corp.intel.com (10.19.9.52) with Microsoft SMTP Server (TLS) id 14.3.123.3; Thu, 24 Apr 2014 02:44:32 -0700 Received: from bgsmsx103.gar.corp.intel.com ([169.254.4.230]) by BGSMSX102.gar.corp.intel.com ([169.254.2.28]) with mapi id 14.03.0123.003; Thu, 24 Apr 2014 15:14:30 +0530 From: "Goel, Akash" To: "chris@chris-wilson.co.uk" Thread-Topic: [PATCH v3] drm/i915: Added write-enable pte bit support Thread-Index: AQHPJwXfr2q1Znf+20+jc4VvB3D1zZsg9RTw Date: Thu, 24 Apr 2014 09:44:28 +0000 Message-ID: <8BF5CF93467D8C498F250C96583BC09CC94D5A@BGSMSX103.gar.corp.intel.com> References: <1392108543-31552-1-git-send-email-akash.goel@intel.com> In-Reply-To: <1392108543-31552-1-git-send-email-akash.goel@intel.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-originating-ip: [10.223.10.10] MIME-Version: 1.0 Cc: "intel-gfx@lists.freedesktop.org" Subject: Re: [Intel-gfx] [PATCH v3] drm/i915: Added write-enable pte bit support X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Spam-Status: No, score=-4.8 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_MED, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Hi Chris, Gentle reminder, Please can you review this patch, have address the review comments. Best Regards Akash -----Original Message----- From: Goel, Akash Sent: Tuesday, February 11, 2014 2:19 PM To: intel-gfx@lists.freedesktop.org Cc: Goel, Akash Subject: [PATCH v3] drm/i915: Added write-enable pte bit support From: Akash Goel This adds support for a write-enable bit in the entry of GTT. This is handled via a read-only flag in the GEM buffer object which is then used to see how to set the bit when writing the GTT entries. Currently by default the Batch buffer & Ring buffers are marked as read only. v2: Moved the pte override code for read-only bit to 'byt_pte_encode'. (Chris) Fixed the issue of leaving 'gt_old_ro' as unused. (Chris) v3: Removed the 'gt_old_ro' field, now setting RO bit only for Ring Buffers(Daniel). Signed-off-by: Akash Goel --- drivers/gpu/drm/i915/i915_drv.h | 6 ++++++ drivers/gpu/drm/i915/i915_gem_gtt.c | 14 ++++++++++++++ drivers/gpu/drm/i915/intel_ringbuffer.c | 3 +++ 3 files changed, 23 insertions(+) -- 1.8.5.2 diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index 728b9c3..8dab62e 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -1699,6 +1699,12 @@ struct drm_i915_gem_object { unsigned int pin_display:1; /* + * Is the object to be mapped as read-only to the GPU + * Only honoured if hardware has relevant pte bit + */ + unsigned long gt_ro:1; + + /* * Is the GPU currently using a fence to access this buffer, */ unsigned int pending_fenced_gpu_access:1; diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c index 6e858e1..1e02d44 100644 --- a/drivers/gpu/drm/i915/i915_gem_gtt.c +++ b/drivers/gpu/drm/i915/i915_gem_gtt.c @@ -151,6 +151,7 @@ static gen6_gtt_pte_t ivb_pte_encode(dma_addr_t addr, #define BYT_PTE_WRITEABLE (1 << 1) #define BYT_PTE_SNOOPED_BY_CPU_CACHES (1 << 2) +#define BYT_PTE_READ_ONLY (1 << 31) static gen6_gtt_pte_t byt_pte_encode(dma_addr_t addr, enum i915_cache_level level, @@ -167,6 +168,10 @@ static gen6_gtt_pte_t byt_pte_encode(dma_addr_t addr, if (level != I915_CACHE_NONE) pte |= BYT_PTE_SNOOPED_BY_CPU_CACHES; + /* Handle read-only request */ + if (level & BYT_PTE_READ_ONLY) + pte &= ~BYT_PTE_WRITEABLE; + return pte; } @@ -810,6 +815,7 @@ static void gen6_ppgtt_insert_entries(struct i915_address_space *vm, pt_vaddr[act_pte] = vm->pte_encode(sg_page_iter_dma_address(&sg_iter), cache_level, true); + if (++act_pte == I915_PPGTT_PT_ENTRIES) { kunmap_atomic(pt_vaddr); pt_vaddr = NULL; @@ -999,6 +1005,10 @@ ppgtt_bind_vma(struct i915_vma *vma, WARN_ON(flags); + if (IS_VALLEYVIEW(vma->vm->dev)) + if (vma->obj->gt_ro) + cache_level |= BYT_PTE_READ_ONLY; + vma->vm->insert_entries(vma->vm, vma->obj->pages, entry, cache_level); } @@ -1336,6 +1346,10 @@ static void ggtt_bind_vma(struct i915_vma *vma, struct drm_i915_gem_object *obj = vma->obj; const unsigned long entry = vma->node.start >> PAGE_SHIFT; + if (IS_VALLEYVIEW(dev)) + if (obj->gt_ro) + cache_level |= BYT_PTE_READ_ONLY; + /* If there is no aliasing PPGTT, or the caller needs a global mapping, * or we have a global mapping already but the cacheability flags have * changed, set the global PTEs. diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c index d897a19..2fee914 100644 --- a/drivers/gpu/drm/i915/intel_ringbuffer.c +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c @@ -1354,6 +1354,9 @@ static int intel_init_ring_buffer(struct drm_device *dev, goto err_hws; } + /* mark ring buffers as read-only from GPU side by default */ + obj->gt_ro = 1; + ring->obj = obj; ret = i915_gem_obj_ggtt_pin(obj, PAGE_SIZE, true, false);