| Message ID | 8a6fc84dadbf1b67fd72f7e7d5a911aa0e6bb510.1629310010.git.jani.nikula@intel.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | drm/i915/dp: dp 2.0 enabling prep work | expand |
On Wed, Aug 18, 2021 at 09:10:41PM +0300, Jani Nikula wrote: > See if sink supports DP 2.0 128b/132b channel encoding, and update sink > rates accordingly. > > FIXME: Also take LTTPR 128b/132b into account. > > Reviewed-by: Manasi Navare <manasi.d.navare@intel.com> > Signed-off-by: Jani Nikula <jani.nikula@intel.com> > --- > drivers/gpu/drm/i915/display/intel_dp.c | 18 ++++++++++++++++++ > 1 file changed, 18 insertions(+) > > diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c > index d273b3848785..079b5b37b85a 100644 > --- a/drivers/gpu/drm/i915/display/intel_dp.c > +++ b/drivers/gpu/drm/i915/display/intel_dp.c > @@ -141,6 +141,24 @@ static void intel_dp_set_sink_rates(struct intel_dp *intel_dp) > intel_dp->sink_rates[i] = dp_rates[i]; > } > > + /* > + * Sink rates for 128b/132b. If set, sink should support all 8b/10b > + * rates and 10 Gbps. > + */ > + if (intel_dp->dpcd[DP_MAIN_LINK_CHANNEL_CODING] & DP_CAP_ANSI_128B132B) { > + u8 uhbr_rates = 0; > + > + drm_dp_dpcd_readb(&intel_dp->aux, > + DP_128B132B_SUPPORTED_LINK_RATES, &uhbr_rates); > + > + if (uhbr_rates & DP_UHBR10) > + intel_dp->sink_rates[i++] = 1000000; > + if (uhbr_rates & DP_UHBR13_5) > + intel_dp->sink_rates[i++] = 1350000; > + if (uhbr_rates & DP_UHBR20) > + intel_dp->sink_rates[i++] = 2000000; OK, so the max link rate register isn't supposed to report the new magic UHBR BW values it seems. That makes life a bit easier. Maybe toss in a BUILD_BUG_ON(ARRAY_SIZE(sink_rates) >= ARRAY_SIZE(dp_rates)+3); or something to remind people that we are dealing with a fixed size array here? Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> > + } > + > intel_dp->num_sink_rates = i; > } > > -- > 2.20.1
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c index d273b3848785..079b5b37b85a 100644 --- a/drivers/gpu/drm/i915/display/intel_dp.c +++ b/drivers/gpu/drm/i915/display/intel_dp.c @@ -141,6 +141,24 @@ static void intel_dp_set_sink_rates(struct intel_dp *intel_dp) intel_dp->sink_rates[i] = dp_rates[i]; } + /* + * Sink rates for 128b/132b. If set, sink should support all 8b/10b + * rates and 10 Gbps. + */ + if (intel_dp->dpcd[DP_MAIN_LINK_CHANNEL_CODING] & DP_CAP_ANSI_128B132B) { + u8 uhbr_rates = 0; + + drm_dp_dpcd_readb(&intel_dp->aux, + DP_128B132B_SUPPORTED_LINK_RATES, &uhbr_rates); + + if (uhbr_rates & DP_UHBR10) + intel_dp->sink_rates[i++] = 1000000; + if (uhbr_rates & DP_UHBR13_5) + intel_dp->sink_rates[i++] = 1350000; + if (uhbr_rates & DP_UHBR20) + intel_dp->sink_rates[i++] = 2000000; + } + intel_dp->num_sink_rates = i; }