From patchwork Tue Aug 7 14:28:45 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: minskey guo X-Patchwork-Id: 1285971 Return-Path: X-Original-To: patchwork-intel-gfx@patchwork.kernel.org Delivered-To: patchwork-process-083081@patchwork2.kernel.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) by patchwork2.kernel.org (Postfix) with ESMTP id 96E32DF280 for ; Tue, 7 Aug 2012 14:29:17 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 84AEA9E96B for ; Tue, 7 Aug 2012 07:29:17 -0700 (PDT) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga11.intel.com (mga11.intel.com [192.55.52.93]) by gabe.freedesktop.org (Postfix) with ESMTP id EEE519E75F for ; Tue, 7 Aug 2012 07:28:49 -0700 (PDT) Received: from fmsmga002.fm.intel.com ([10.253.24.26]) by fmsmga102.fm.intel.com with ESMTP; 07 Aug 2012 07:28:49 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="4.71,315,1320652800"; d="scan'208";a="204110798" Received: from fmsmsx104.amr.corp.intel.com ([10.19.9.35]) by fmsmga002.fm.intel.com with ESMTP; 07 Aug 2012 07:28:49 -0700 Received: from fmsmsx152.amr.corp.intel.com (10.19.17.221) by FMSMSX104.amr.corp.intel.com (10.19.9.35) with Microsoft SMTP Server (TLS) id 14.1.355.2; Tue, 7 Aug 2012 07:28:49 -0700 Received: from shsmsx101.ccr.corp.intel.com (10.239.4.153) by fmsmsx152.amr.corp.intel.com (10.19.17.221) with Microsoft SMTP Server (TLS) id 14.1.355.2; Tue, 7 Aug 2012 07:28:49 -0700 Received: from shsmsx102.ccr.corp.intel.com ([169.254.2.196]) by SHSMSX101.ccr.corp.intel.com ([169.254.1.82]) with mapi id 14.01.0355.002; Tue, 7 Aug 2012 22:28:46 +0800 From: "Guo, Chaohong" To: Paulo Zanoni Thread-Topic: [Intel-gfx] [PATCH ddx] Add Haswell PCI IDs Thread-Index: AQHNdB2xnKgRn4JlnUuDP6nbu6lAJ5dOaKaw Date: Tue, 7 Aug 2012 14:28:45 +0000 Message-ID: References: <1344289689-5166-1-git-send-email-przanoni@gmail.com> In-Reply-To: <1344289689-5166-1-git-send-email-przanoni@gmail.com> Accept-Language: zh-CN, en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-originating-ip: [10.239.127.40] MIME-Version: 1.0 Cc: "intel-gfx@lists.freedesktop.org" , "Zanoni, Paulo R" Subject: Re: [Intel-gfx] [PATCH ddx] Add Haswell PCI IDs X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.13 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: intel-gfx-bounces+patchwork-intel-gfx=patchwork.kernel.org@lists.freedesktop.org Errors-To: intel-gfx-bounces+patchwork-intel-gfx=patchwork.kernel.org@lists.freedesktop.org Why using "xxx_SDV_xxx" in the macros ? Is there an official Name for those chips ? Besides, what does "CRW" stands For ? Thanks, -minskey -----Original Message----- From: intel-gfx-bounces+chaohong.guo=intel.com@lists.freedesktop.org [mailto:intel-gfx-bounces+chaohong.guo=intel.com@lists.freedesktop.org] On Behalf Of Paulo Zanoni Sent: Tuesday, August 07, 2012 5:48 AM To: intel-gfx@lists.freedesktop.org Cc: Zanoni, Paulo R Subject: [Intel-gfx] [PATCH ddx] Add Haswell PCI IDs From: Paulo Zanoni Signed-off-by: Paulo Zanoni --- src/intel_driver.h | 37 +++++++++++++++++++++++++++ src/intel_module.c | 73 ++++++++++++++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 110 insertions(+) INTEL_DEVICE_MATCH (PCI_CHIP_IVYBRIDGE_S_GT1, &intel_ivybridge_info ), INTEL_DEVICE_MATCH (PCI_CHIP_IVYBRIDGE_S_GT2, &intel_ivybridge_info ), + INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_D_GT1, &intel_haswell_info ), + INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_D_GT2, &intel_haswell_info ), + INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_D_GT2_PLUS, &intel_haswell_info ), + INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_M_GT1, &intel_haswell_info ), + INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_M_GT2, &intel_haswell_info ), + INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_M_GT2_PLUS, &intel_haswell_info ), + INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_S_GT1, &intel_haswell_info ), + INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_S_GT2, &intel_haswell_info ), + INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_S_GT2_PLUS, &intel_haswell_info ), + INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_SDV_D_GT1, &intel_haswell_info ), + INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_SDV_D_GT2, &intel_haswell_info ), + INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_SDV_D_GT2_PLUS, &intel_haswell_info ), + INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_SDV_M_GT1, &intel_haswell_info ), + INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_SDV_M_GT2, &intel_haswell_info ), + INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_SDV_M_GT2_PLUS, &intel_haswell_info ), + INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_SDV_S_GT1, &intel_haswell_info ), + INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_SDV_S_GT2, &intel_haswell_info ), + INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_SDV_S_GT2_PLUS, &intel_haswell_info ), + INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_ULT_D_GT1, &intel_haswell_info ), + INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_ULT_D_GT2, &intel_haswell_info ), + INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_ULT_D_GT2_PLUS, &intel_haswell_info ), + INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_ULT_M_GT1, &intel_haswell_info ), + INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_ULT_M_GT2, &intel_haswell_info ), + INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_ULT_M_GT2_PLUS, &intel_haswell_info ), + INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_ULT_S_GT1, &intel_haswell_info ), + INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_ULT_S_GT2, &intel_haswell_info ), + INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_ULT_S_GT2_PLUS, &intel_haswell_info ), + INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_CRW_D_GT1, &intel_haswell_info ), + INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_CRW_D_GT2, &intel_haswell_info ), + INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_CRW_D_GT2_PLUS, &intel_haswell_info ), + INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_CRW_M_GT1, &intel_haswell_info ), + INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_CRW_M_GT2, &intel_haswell_info ), + INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_CRW_M_GT2_PLUS, &intel_haswell_info ), + INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_CRW_S_GT1, &intel_haswell_info ), + INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_CRW_S_GT2, &intel_haswell_info ), + INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_CRW_S_GT2_PLUS, +&intel_haswell_info ), + INTEL_DEVICE_MATCH (PCI_MATCH_ANY, &intel_generic_info ), { 0, 0, 0 }, }; -- 1.7.11.2 diff --git a/src/intel_driver.h b/src/intel_driver.h index 882d889..ac02cc7 100644 --- a/src/intel_driver.h +++ b/src/intel_driver.h @@ -192,6 +192,43 @@ #define PCI_CHIP_IVYBRIDGE_S_GT1 0x015a #define PCI_CHIP_IVYBRIDGE_S_GT2 0x016a +#define PCI_CHIP_HASWELL_D_GT1 0x0402 +#define PCI_CHIP_HASWELL_D_GT2 0x0412 +#define PCI_CHIP_HASWELL_D_GT2_PLUS 0x0422 +#define PCI_CHIP_HASWELL_M_GT1 0x0406 +#define PCI_CHIP_HASWELL_M_GT2 0x0416 +#define PCI_CHIP_HASWELL_M_GT2_PLUS 0x0426 +#define PCI_CHIP_HASWELL_S_GT1 0x040A +#define PCI_CHIP_HASWELL_S_GT2 0x041A +#define PCI_CHIP_HASWELL_S_GT2_PLUS 0x042A +#define PCI_CHIP_HASWELL_SDV_D_GT1 0x0C02 +#define PCI_CHIP_HASWELL_SDV_D_GT2 0x0C12 +#define PCI_CHIP_HASWELL_SDV_D_GT2_PLUS 0x0C22 +#define PCI_CHIP_HASWELL_SDV_M_GT1 0x0C06 +#define PCI_CHIP_HASWELL_SDV_M_GT2 0x0C16 +#define PCI_CHIP_HASWELL_SDV_M_GT2_PLUS 0x0C26 +#define PCI_CHIP_HASWELL_SDV_S_GT1 0x0C0A +#define PCI_CHIP_HASWELL_SDV_S_GT2 0x0C1A +#define PCI_CHIP_HASWELL_SDV_S_GT2_PLUS 0x0C2A +#define PCI_CHIP_HASWELL_ULT_D_GT1 0x0A02 +#define PCI_CHIP_HASWELL_ULT_D_GT2 0x0A12 +#define PCI_CHIP_HASWELL_ULT_D_GT2_PLUS 0x0A22 +#define PCI_CHIP_HASWELL_ULT_M_GT1 0x0A06 +#define PCI_CHIP_HASWELL_ULT_M_GT2 0x0A16 +#define PCI_CHIP_HASWELL_ULT_M_GT2_PLUS 0x0A26 +#define PCI_CHIP_HASWELL_ULT_S_GT1 0x0A0A +#define PCI_CHIP_HASWELL_ULT_S_GT2 0x0A1A +#define PCI_CHIP_HASWELL_ULT_S_GT2_PLUS 0x0A2A +#define PCI_CHIP_HASWELL_CRW_D_GT1 0x0D12 +#define PCI_CHIP_HASWELL_CRW_D_GT2 0x0D22 +#define PCI_CHIP_HASWELL_CRW_D_GT2_PLUS 0x0D32 +#define PCI_CHIP_HASWELL_CRW_M_GT1 0x0D16 +#define PCI_CHIP_HASWELL_CRW_M_GT2 0x0D26 +#define PCI_CHIP_HASWELL_CRW_M_GT2_PLUS 0x0D36 +#define PCI_CHIP_HASWELL_CRW_S_GT1 0x0D1A +#define PCI_CHIP_HASWELL_CRW_S_GT2 0x0D2A +#define PCI_CHIP_HASWELL_CRW_S_GT2_PLUS 0x0D3A + #endif #define I85X_CAPID 0x44 diff --git a/src/intel_module.c b/src/intel_module.c index ae19f75..c0403ca 100644 --- a/src/intel_module.c +++ b/src/intel_module.c @@ -149,6 +149,42 @@ static const SymTabRec _intel_chipsets[] = { {PCI_CHIP_IVYBRIDGE_D_GT2, "Ivybridge Desktop (GT2)" }, {PCI_CHIP_IVYBRIDGE_S_GT1, "Ivybridge Server" }, {PCI_CHIP_IVYBRIDGE_S_GT2, "Ivybridge Server (GT2)" }, + {PCI_CHIP_HASWELL_D_GT1, "Haswell Desktop (GT1)" }, + {PCI_CHIP_HASWELL_D_GT2, "Haswell Desktop (GT2)" }, + {PCI_CHIP_HASWELL_D_GT2_PLUS, "Haswell Desktop (GT2+)" }, + {PCI_CHIP_HASWELL_M_GT1, "Haswell Mobile (GT1)" }, + {PCI_CHIP_HASWELL_M_GT2, "Haswell Mobile (GT2)" }, + {PCI_CHIP_HASWELL_M_GT2_PLUS, "Haswell Mobile (GT2+)" }, + {PCI_CHIP_HASWELL_S_GT1, "Haswell Server (GT1)" }, + {PCI_CHIP_HASWELL_S_GT2, "Haswell Server (GT2)" }, + {PCI_CHIP_HASWELL_S_GT2_PLUS, "Haswell Server (GT2+)" }, + {PCI_CHIP_HASWELL_SDV_D_GT1, "Haswell SDV Desktop (GT1)" }, + {PCI_CHIP_HASWELL_SDV_D_GT2, "Haswell SDV Desktop (GT2)" }, + {PCI_CHIP_HASWELL_SDV_D_GT2_PLUS, "Haswell SDV Desktop (GT2+)" }, + {PCI_CHIP_HASWELL_SDV_M_GT1, "Haswell SDV Mobile (GT1)" }, + {PCI_CHIP_HASWELL_SDV_M_GT2, "Haswell SDV Mobile (GT2)" }, + {PCI_CHIP_HASWELL_SDV_M_GT2_PLUS, "Haswell SDV Mobile (GT2+)" }, + {PCI_CHIP_HASWELL_SDV_S_GT1, "Haswell SDV Server (GT1)" }, + {PCI_CHIP_HASWELL_SDV_S_GT2, "Haswell SDV Server (GT2)" }, + {PCI_CHIP_HASWELL_SDV_S_GT2_PLUS, "Haswell SDV Server (GT2+)" }, + {PCI_CHIP_HASWELL_ULT_D_GT1, "Haswell ULT Desktop (GT1)" }, + {PCI_CHIP_HASWELL_ULT_D_GT2, "Haswell ULT Desktop (GT2)" }, + {PCI_CHIP_HASWELL_ULT_D_GT2_PLUS, "Haswell ULT Desktop (GT2+)" }, + {PCI_CHIP_HASWELL_ULT_M_GT1, "Haswell ULT Mobile (GT1)" }, + {PCI_CHIP_HASWELL_ULT_M_GT2, "Haswell ULT Mobile (GT2)" }, + {PCI_CHIP_HASWELL_ULT_M_GT2_PLUS, "Haswell ULT Mobile (GT2+)" }, + {PCI_CHIP_HASWELL_ULT_S_GT1, "Haswell ULT Server (GT1)" }, + {PCI_CHIP_HASWELL_ULT_S_GT2, "Haswell ULT Server (GT2)" }, + {PCI_CHIP_HASWELL_ULT_S_GT2_PLUS, "Haswell ULT Server (GT2+)" }, + {PCI_CHIP_HASWELL_CRW_D_GT1, "Haswell CRW Desktop (GT1)" }, + {PCI_CHIP_HASWELL_CRW_D_GT2, "Haswell CRW Desktop (GT2)" }, + {PCI_CHIP_HASWELL_CRW_D_GT2_PLUS, "Haswell CRW Desktop (GT2+)" }, + {PCI_CHIP_HASWELL_CRW_M_GT1, "Haswell CRW Mobile (GT1)" }, + {PCI_CHIP_HASWELL_CRW_M_GT2, "Haswell CRW Mobile (GT2)" }, + {PCI_CHIP_HASWELL_CRW_M_GT2_PLUS, "Haswell CRW Mobile (GT2+)" }, + {PCI_CHIP_HASWELL_CRW_S_GT1, "Haswell CRW Server (GT1)" }, + {PCI_CHIP_HASWELL_CRW_S_GT2, "Haswell CRW Server (GT2)" }, + {PCI_CHIP_HASWELL_CRW_S_GT2_PLUS, "Haswell CRW Server (GT2+)" }, {-1, NULL} }; #define NUM_CHIPSETS (sizeof(_intel_chipsets) / sizeof(_intel_chipsets[0])) @@ -221,6 +257,43 @@ static const struct pci_id_match intel_device_match[] = {