diff mbox

[2/2] drm/i915/vlv: use parallel context restore when coming out of RC6

Message ID F359EE24E0B97E4A9739736D2C188EF3FB1641@BGSMSX102.gar.corp.intel.com (mailing list archive)
State New, archived
Headers show

Commit Message

deepak.s@intel.com Nov. 28, 2013, 8:17 a.m. UTC 
Patches looks fine.

Reviewed-by: Deepak S <deepak.s@inel.com<mailto:jbarnes@virtuousgeek.org>>


From: Jesse Barnes <jbarnes@virtuousgeek.org<mailto:jbarnes@virtuousgeek.org>>
Date: Fri, Nov 15, 2013 at 11:02 PM
Subject: [Intel-gfx] [PATCH 2/2] drm/i915/vlv: use parallel context restore when coming out of RC6
To: intel-gfx@lists.freedesktop.org<mailto:intel-gfx@lists.freedesktop.org>


Setting this bit restores all ring contexts in parallel rather than
serially.  Matches current BWG recommendations.

Tested-by: "Meng, Mengmeng" <mengmeng.meng@intel.com<mailto:mengmeng.meng@intel.com>>
Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org<mailto:jbarnes@virtuousgeek.org>>
---
 drivers/gpu/drm/i915/i915_reg.h | 1 +
 drivers/gpu/drm/i915/intel_pm.c | 2 +-
 2 files changed, 2 insertions(+), 1 deletion(-)

--
1.8.4.2

Comments

Daniel Vetter Nov. 28, 2013, 10:03 a.m. UTC | #1 
On Thu, Nov 28, 2013 at 08:17:08AM +0000, S, Deepak wrote:
> Patches looks fine.
> 
> Reviewed-by: Deepak S <deepak.s@inel.com<mailto:jbarnes@virtuousgeek.org>>

Both merged, thanks for patches&review. Aside: Your mail is html
multipart formatted which creates some good fun with your r-b tag ;-)
Plain text preferrred.
-Daniel
diff mbox

Patch

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 849e595..40b1136 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -4891,6 +4891,7 @@ 
 #define   GEN6_RC_CTL_RC6_ENABLE               (1<<18)
 #define   GEN6_RC_CTL_RC1e_ENABLE              (1<<20)
 #define   GEN6_RC_CTL_RC7_ENABLE               (1<<22)
+#define   VLV_RC_CTL_CTX_RST_PARALLEL          (1<<24)
 #define   GEN7_RC_CTL_TO_MODE                  (1<<28)
 #define   GEN6_RC_CTL_EI_MODE(x)               ((x)<<27)
 #define   GEN6_RC_CTL_HW_ENABLE                        (1<<31)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 5d3912a..6a21d11 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -4110,7 +4110,7 @@  static void valleyview_enable_rps(struct drm_device *dev)
                                      VLV_MEDIA_RC6_COUNT_EN |
                                      VLV_RENDER_RC6_COUNT_EN));
        if (intel_enable_rc6(dev) & INTEL_RC6_ENABLE)
-               rc6_mode = GEN7_RC_CTL_TO_MODE;
+               rc6_mode = GEN7_RC_CTL_TO_MODE | VLV_RC_CTL_CTX_RST_PARALLEL;

        intel_print_rc6_info(dev, rc6_mode);