From patchwork Fri Mar 26 13:21:33 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Jani Nikula X-Patchwork-Id: 12166621 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.8 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 9A479C433C1 for ; Fri, 26 Mar 2021 13:21:58 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 3A7AD61A06 for ; Fri, 26 Mar 2021 13:21:58 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 3A7AD61A06 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=intel.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=intel-gfx-bounces@lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id BCB866F3D0; Fri, 26 Mar 2021 13:21:57 +0000 (UTC) Received: from mga11.intel.com (mga11.intel.com [192.55.52.93]) by gabe.freedesktop.org (Postfix) with ESMTPS id 0F3F76F3D0 for ; Fri, 26 Mar 2021 13:21:57 +0000 (UTC) IronPort-SDR: OelCu17690g9JmNZz2JFTc7k5VNMfdH7WbDc1sXLTnzFMsfJuCYxHjhYPU0txXhydcrGqo/KDw 1cPYQKcdQSVg== X-IronPort-AV: E=McAfee;i="6000,8403,9934"; a="187858190" X-IronPort-AV: E=Sophos;i="5.81,280,1610438400"; d="scan'208";a="187858190" Received: from fmsmga008.fm.intel.com ([10.253.24.58]) by fmsmga102.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 26 Mar 2021 06:21:56 -0700 IronPort-SDR: mfsjvbrsJXC3ThLPFUzhQkpRPdyuTNd6AG15sjbvAlRdTVQBqZ0qDr9q0sHedSHvDRYqEbgQ0M tMb4F3x8aGdA== X-IronPort-AV: E=Sophos;i="5.81,280,1610438400"; d="scan'208";a="409896408" Received: from mpaulits-mobl1.ger.corp.intel.com (HELO localhost) ([10.252.55.191]) by fmsmga008-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 26 Mar 2021 06:21:54 -0700 From: Jani Nikula To: intel-gfx@lists.freedesktop.org Date: Fri, 26 Mar 2021 15:21:33 +0200 Message-Id: X-Mailer: git-send-email 2.20.1 In-Reply-To: References: MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH v4 2/7] drm/i915: add new helpers for accessing stepping info X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: jani.nikula@intel.com Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" Add new runtime info field for stepping. Add new helpers for accessing them. As we'll be switching platforms over to the new scheme incrementally, check for non-initialized steppings. In case a platform does not have separate display and gt steppings, it's okay to use a common shorthand. However, in this case the display stepping must not be initialized, and gt stepping is the single point of truth. v3: Remove IS_STEP() (José) v2: Rename stepping->step Reviewed-by: José Roberto de Souza Signed-off-by: Jani Nikula --- drivers/gpu/drm/i915/i915_drv.h | 20 +++++++++++--------- drivers/gpu/drm/i915/intel_device_info.h | 4 ++++ drivers/gpu/drm/i915/intel_step.h | 14 ++++++++++++++ 3 files changed, 29 insertions(+), 9 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index 3fcba7d93db7..380088fd6dcf 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -1268,6 +1268,17 @@ static inline struct drm_i915_private *pdev_to_i915(struct pci_dev *pdev) #define IS_REVID(p, since, until) \ (INTEL_REVID(p) >= (since) && INTEL_REVID(p) <= (until)) +#define INTEL_DISPLAY_STEP(__i915) (RUNTIME_INFO(__i915)->step.disp_stepping) +#define INTEL_GT_STEP(__i915) (RUNTIME_INFO(__i915)->step.gt_stepping) + +#define IS_DISPLAY_STEP(__i915, since, until) \ + (drm_WARN_ON(&(__i915)->drm, INTEL_DISPLAY_STEP(__i915) == STEP_NONE), \ + INTEL_DISPLAY_STEP(__i915) >= (since) && INTEL_DISPLAY_STEP(__i915) <= (until)) + +#define IS_GT_STEP(__i915, since, until) \ + (drm_WARN_ON(&(__i915)->drm, INTEL_GT_STEP(__i915) == STEP_NONE), \ + INTEL_GT_STEP(__i915) >= (since) && INTEL_GT_STEP(__i915) <= (until)) + static __always_inline unsigned int __platform_mask_index(const struct intel_runtime_info *info, enum intel_platform p) @@ -1506,15 +1517,6 @@ enum { #define IS_JSL_EHL_REVID(p, since, until) \ (IS_JSL_EHL(p) && IS_REVID(p, since, until)) -enum { - STEP_A0, - STEP_A2, - STEP_B0, - STEP_B1, - STEP_C0, - STEP_D0, -}; - static inline const struct i915_rev_steppings * tgl_stepping_get(struct drm_i915_private *dev_priv) { diff --git a/drivers/gpu/drm/i915/intel_device_info.h b/drivers/gpu/drm/i915/intel_device_info.h index 90acbaf800d5..e410635cb4ea 100644 --- a/drivers/gpu/drm/i915/intel_device_info.h +++ b/drivers/gpu/drm/i915/intel_device_info.h @@ -27,6 +27,8 @@ #include +#include "intel_step.h" + #include "display/intel_display.h" #include "gt/intel_engine_types.h" @@ -227,6 +229,8 @@ struct intel_runtime_info { u8 num_scalers[I915_MAX_PIPES]; u32 rawclk_freq; + + struct i915_rev_steppings step; }; struct intel_driver_caps { diff --git a/drivers/gpu/drm/i915/intel_step.h b/drivers/gpu/drm/i915/intel_step.h index af922ae3bb4e..8b3ef19d935b 100644 --- a/drivers/gpu/drm/i915/intel_step.h +++ b/drivers/gpu/drm/i915/intel_step.h @@ -22,4 +22,18 @@ extern const struct i915_rev_steppings tgl_uy_revid_step_tbl[TGL_UY_REVID_STEP_T extern const struct i915_rev_steppings tgl_revid_step_tbl[TGL_REVID_STEP_TBL_SIZE]; extern const struct i915_rev_steppings adls_revid_step_tbl[ADLS_REVID_STEP_TBL_SIZE]; +/* + * Symbolic steppings that do not match the hardware. These are valid both as gt + * and display steppings as symbolic names. + */ +enum intel_step { + STEP_NONE = 0, + STEP_A0, + STEP_A2, + STEP_B0, + STEP_B1, + STEP_C0, + STEP_D0, +}; + #endif /* __INTEL_STEP_H__ */