| Message ID | bc1972391041a3ba84b3f68b9c0605ae142611e0.1738327620.git.jani.nikula@intel.com (mailing list archive) |
|---|---|
| State | New |
| Headers | show |
| Series | drm/i915/dp: dsc fix, refactoring and cleanups | expand |
On Fri, Jan 31, 2025 at 02:49:59PM +0200, Jani Nikula wrote: > Instead of iterating the valid BPP array directly, switch to the same > approach as xelpd_dsc_compute_link_config(), with a separate function to > check if the DSC BPP is valid. This prepares us for unifying the > platform specific functions. > > Signed-off-by: Jani Nikula <jani.nikula@intel.com> Reviewed-by: Imre Deak <imre.deak@intel.com> > --- > drivers/gpu/drm/i915/display/intel_dp.c | 33 +++++++++++++++++++------ > 1 file changed, 26 insertions(+), 7 deletions(-) > > diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c > index 4e7b3dd4067c..ac67f2d2f86a 100644 > --- a/drivers/gpu/drm/i915/display/intel_dp.c > +++ b/drivers/gpu/drm/i915/display/intel_dp.c > @@ -2069,6 +2069,26 @@ static int intel_dp_dsc_bpp_step_x16(const struct intel_connector *connector) > return 16 / incr; > } > > +/* Note: This is not universally usable! */ > +static bool intel_dp_dsc_valid_bpp(struct intel_dp *intel_dp, int bpp_x16) > +{ > + struct intel_display *display = to_intel_display(intel_dp); > + int i; > + > + if (DISPLAY_VER(display) >= 13) > + return true; > + > + if (fxp_q4_to_frac(bpp_x16)) > + return false; > + > + for (i = 0; i < ARRAY_SIZE(valid_dsc_bpp); i++) { > + if (fxp_q4_to_int(bpp_x16) == valid_dsc_bpp[i]) > + return true; > + } > + > + return false; > +} > + > /* > * From a list of valid compressed bpps try different compressed bpp and find a > * suitable link configuration that can support it. > @@ -2082,21 +2102,20 @@ icl_dsc_compute_link_config(struct intel_dp *intel_dp, > int bpp_step_x16, > int timeslots) > { > - int i, ret; > + int bpp_x16; > + int ret; > > - for (i = ARRAY_SIZE(valid_dsc_bpp) - 1; i >= 0; i--) { > - if (valid_dsc_bpp[i] < fxp_q4_to_int(min_bpp_x16) || > - valid_dsc_bpp[i] > fxp_q4_to_int(max_bpp_x16)) > + for (bpp_x16 = max_bpp_x16; bpp_x16 >= min_bpp_x16; bpp_x16 -= bpp_step_x16) { > + if (!intel_dp_dsc_valid_bpp(intel_dp, bpp_x16)) > continue; > > ret = dsc_compute_link_config(intel_dp, > pipe_config, > limits, > - valid_dsc_bpp[i] << 4, > + bpp_x16, > timeslots); > if (ret == 0) { > - pipe_config->dsc.compressed_bpp_x16 = > - fxp_q4_from_int(valid_dsc_bpp[i]); > + pipe_config->dsc.compressed_bpp_x16 = bpp_x16; > return 0; > } > } > -- > 2.39.5 >
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c index 4e7b3dd4067c..ac67f2d2f86a 100644 --- a/drivers/gpu/drm/i915/display/intel_dp.c +++ b/drivers/gpu/drm/i915/display/intel_dp.c @@ -2069,6 +2069,26 @@ static int intel_dp_dsc_bpp_step_x16(const struct intel_connector *connector) return 16 / incr; } +/* Note: This is not universally usable! */ +static bool intel_dp_dsc_valid_bpp(struct intel_dp *intel_dp, int bpp_x16) +{ + struct intel_display *display = to_intel_display(intel_dp); + int i; + + if (DISPLAY_VER(display) >= 13) + return true; + + if (fxp_q4_to_frac(bpp_x16)) + return false; + + for (i = 0; i < ARRAY_SIZE(valid_dsc_bpp); i++) { + if (fxp_q4_to_int(bpp_x16) == valid_dsc_bpp[i]) + return true; + } + + return false; +} + /* * From a list of valid compressed bpps try different compressed bpp and find a * suitable link configuration that can support it. @@ -2082,21 +2102,20 @@ icl_dsc_compute_link_config(struct intel_dp *intel_dp, int bpp_step_x16, int timeslots) { - int i, ret; + int bpp_x16; + int ret; - for (i = ARRAY_SIZE(valid_dsc_bpp) - 1; i >= 0; i--) { - if (valid_dsc_bpp[i] < fxp_q4_to_int(min_bpp_x16) || - valid_dsc_bpp[i] > fxp_q4_to_int(max_bpp_x16)) + for (bpp_x16 = max_bpp_x16; bpp_x16 >= min_bpp_x16; bpp_x16 -= bpp_step_x16) { + if (!intel_dp_dsc_valid_bpp(intel_dp, bpp_x16)) continue; ret = dsc_compute_link_config(intel_dp, pipe_config, limits, - valid_dsc_bpp[i] << 4, + bpp_x16, timeslots); if (ret == 0) { - pipe_config->dsc.compressed_bpp_x16 = - fxp_q4_from_int(valid_dsc_bpp[i]); + pipe_config->dsc.compressed_bpp_x16 = bpp_x16; return 0; } }
Instead of iterating the valid BPP array directly, switch to the same approach as xelpd_dsc_compute_link_config(), with a separate function to check if the DSC BPP is valid. This prepares us for unifying the platform specific functions. Signed-off-by: Jani Nikula <jani.nikula@intel.com> --- drivers/gpu/drm/i915/display/intel_dp.c | 33 +++++++++++++++++++------ 1 file changed, 26 insertions(+), 7 deletions(-)