[19/39] drm/i915: move and group sagv under display.sagv

Message ID	d5c0376475b3aacba392a243df00416dda32ec5e.1660230121.git.jani.nikula@intel.com (mailing list archive)
State	New, archived
Headers	show Return-Path: <intel-gfx-bounces@lists.freedesktop.org> From: Jani Nikula <jani.nikula@intel.com> To: intel-gfx@lists.freedesktop.org Date: Thu, 11 Aug 2022 18:07:30 +0300 Message-Id: <d5c0376475b3aacba392a243df00416dda32ec5e.1660230121.git.jani.nikula@intel.com> In-Reply-To: <cover.1660230121.git.jani.nikula@intel.com> References: <cover.1660230121.git.jani.nikula@intel.com> MIME-Version: 1.0 Organization: Intel Finland Oy - BIC 0357606-4 - Westendinkatu 7, 02160 Espoo Content-Transfer-Encoding: 8bit Subject: [Intel-gfx] [PATCH 19/39] drm/i915: move and group sagv under display.sagv Precedence: list Cc: jani.nikula@intel.com, lucas.demarchi@intel.com Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" <intel-gfx-bounces@lists.freedesktop.org>
Series	drm/i915: add display sub-struct to drm_i915_private \| expand [00/39] drm/i915: add display sub-struct to drm_i915_private [01/39] drm/i915: add display sub-struct to drm_i915_private [02/39] drm/i915: move cdclk_funcs to display.funcs [03/39] drm/i915: move dpll_funcs to display.funcs [04/39] drm/i915: move hotplug_funcs to display.funcs [05/39] drm/i915: move clock_gating_funcs to display.funcs [06/39] drm/i915: move wm_disp funcs to display.funcs [07/39] drm/i915: move fdi_funcs to display.funcs [08/39] drm/i915: move color_funcs to display.funcs [09/39] drm/i915: move and group gmbus members under display.gmbus [10/39] drm/i915: move and group pps members under display.pps [11/39] drm/i915: move dmc to display.dmc [12/39] drm/i915: move and split audio under display.audio and display.funcs [13/39] drm/i915: move dpll under display.dpll [14/39] drm/i915: move and group fbdev under display.fbdev [15/39] drm/i915: move wm to display.wm [16/39] drm/i915: move and group hdcp under display.hdcp [17/39] drm/i915: move hotplug to display.hotplug [18/39] drm/i915: move overlay to display.overlay [19/39] drm/i915: move and group sagv under display.sagv [20/39] drm/i915: move and group max_bw and bw_obj under display.bw [21/39] drm/i915: move opregion to display.opregion [22/39] drm/i915: move and group cdclk under display.cdclk [23/39] drm/i915: move backlight to display.backlight [24/39] drm/i915: move mipi_mmio_base to display.dsi [25/39] drm/i915: move vbt to display.vbt [26/39] drm/i915: move fbc to display.fbc [27/39] drm/i915/vrr: drop window2_delay member from i915 [28/39] drm/i915: move and group power related members under display.power [29/39] drm/i915: move and group fdi members under display.fdi [30/39] drm/i915: move fb_tracking under display sub-struct [31/39] drm/i915: move INTEL_FRONTBUFFER_* macros to intel_frontbuffer.h [32/39] drm/i915: move dbuf under display sub-struct [33/39] drm/i915: move and group modeset_wq and flip_wq under display.wq [34/39] drm/i915: split gem quirks from display quirks [35/39] drm/i915/quirks: abstract checking for display quirks [36/39] drm/i915/quirks: abstract quirks further by making quirk ids an enum [37/39] drm/i915: move quirks under display sub-struct [38/39] drm/i915: move atomic_helper under display sub-struct [39/39] drm/i915: move and group properties under display.properties

diff --git a/drivers/gpu/drm/i915/display/intel_bw.c b/drivers/gpu/drm/i915/display/intel_bw.c index 79269d2c476b..4e60ad847eb0 100644 --- a/drivers/gpu/drm/i915/display/intel_bw.c +++ b/drivers/gpu/drm/i915/display/intel_bw.c @@ -346,9 +346,9 @@ static int icl_get_bw_info(struct drm_i915_private *dev_priv, const struct intel * as it will fail and pointless anyway. */ if (qi.num_points == 1) - dev_priv->sagv_status = I915_SAGV_NOT_CONTROLLED; + dev_priv->display.sagv.status = I915_SAGV_NOT_CONTROLLED; else - dev_priv->sagv_status = I915_SAGV_ENABLED; + dev_priv->display.sagv.status = I915_SAGV_ENABLED; return 0; } @@ -456,9 +456,9 @@ static int tgl_get_bw_info(struct drm_i915_private *dev_priv, const struct intel * as it will fail and pointless anyway. */ if (qi.num_points == 1) - dev_priv->sagv_status = I915_SAGV_NOT_CONTROLLED; + dev_priv->display.sagv.status = I915_SAGV_NOT_CONTROLLED; else - dev_priv->sagv_status = I915_SAGV_ENABLED; + dev_priv->display.sagv.status = I915_SAGV_ENABLED; return 0; } @@ -485,7 +485,7 @@ static void dg2_get_bw_info(struct drm_i915_private *i915) bi->deratedbw[0] = deratedbw; } - i915->sagv_status = I915_SAGV_NOT_CONTROLLED; + i915->display.sagv.status = I915_SAGV_NOT_CONTROLLED; } static unsigned int icl_max_bw(struct drm_i915_private *dev_priv, diff --git a/drivers/gpu/drm/i915/display/intel_display_core.h b/drivers/gpu/drm/i915/display/intel_display_core.h index a5cd3a3d440e..ab68c8799d1c 100644 --- a/drivers/gpu/drm/i915/display/intel_display_core.h +++ b/drivers/gpu/drm/i915/display/intel_display_core.h @@ -249,6 +249,17 @@ struct intel_display { struct mutex mutex; } pps; + struct { + enum { + I915_SAGV_UNKNOWN = 0, + I915_SAGV_DISABLED, + I915_SAGV_ENABLED, + I915_SAGV_NOT_CONTROLLED + } status; + + u32 block_time_us; + } sagv; + /* Grouping using named structs. Keep sorted. */ struct intel_audio audio; struct intel_dmc dmc; diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index 3637ee4ca088..daa6266ef127 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -447,15 +447,6 @@ struct drm_i915_private { struct i915_suspend_saved_registers regfile; struct vlv_s0ix_state *vlv_s0ix_state; - enum { - I915_SAGV_UNKNOWN = 0, - I915_SAGV_DISABLED, - I915_SAGV_ENABLED, - I915_SAGV_NOT_CONTROLLED - } sagv_status; - - u32 sagv_block_time_us; - struct dram_info { bool wm_lv_0_adjust_needed; u8 num_channels; diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c index 14134e57034e..f72481e85ebd 100644 --- a/drivers/gpu/drm/i915/intel_pm.c +++ b/drivers/gpu/drm/i915/intel_pm.c @@ -3669,7 +3669,7 @@ static bool intel_has_sagv(struct drm_i915_private *dev_priv) { return DISPLAY_VER(dev_priv) >= 9 && !IS_LP(dev_priv) && - dev_priv->sagv_status != I915_SAGV_NOT_CONTROLLED; + dev_priv->display.sagv.status != I915_SAGV_NOT_CONTROLLED; } static u32 @@ -3700,7 +3700,7 @@ intel_sagv_block_time(struct drm_i915_private *dev_priv) static void intel_sagv_init(struct drm_i915_private *i915) { if (!intel_has_sagv(i915)) - i915->sagv_status = I915_SAGV_NOT_CONTROLLED; + i915->display.sagv.status = I915_SAGV_NOT_CONTROLLED; /* * Probe to see if we have working SAGV control. @@ -3709,21 +3709,21 @@ static void intel_sagv_init(struct drm_i915_private *i915) if (DISPLAY_VER(i915) < 11) skl_sagv_disable(i915); - drm_WARN_ON(&i915->drm, i915->sagv_status == I915_SAGV_UNKNOWN); + drm_WARN_ON(&i915->drm, i915->display.sagv.status == I915_SAGV_UNKNOWN); - i915->sagv_block_time_us = intel_sagv_block_time(i915); + i915->display.sagv.block_time_us = intel_sagv_block_time(i915); drm_dbg_kms(&i915->drm, "SAGV supported: %s, original SAGV block time: %u us\n", - str_yes_no(intel_has_sagv(i915)), i915->sagv_block_time_us); + str_yes_no(intel_has_sagv(i915)), i915->display.sagv.block_time_us); /* avoid overflow when adding with wm0 latency/etc. */ - if (drm_WARN(&i915->drm, i915->sagv_block_time_us > U16_MAX, + if (drm_WARN(&i915->drm, i915->display.sagv.block_time_us > U16_MAX, "Excessive SAGV block time %u, ignoring\n", - i915->sagv_block_time_us)) - i915->sagv_block_time_us = 0; + i915->display.sagv.block_time_us)) + i915->display.sagv.block_time_us = 0; if (!intel_has_sagv(i915)) - i915->sagv_block_time_us = 0; + i915->display.sagv.block_time_us = 0; } /* @@ -3744,7 +3744,7 @@ static void skl_sagv_enable(struct drm_i915_private *dev_priv) if (!intel_has_sagv(dev_priv)) return; - if (dev_priv->sagv_status == I915_SAGV_ENABLED) + if (dev_priv->display.sagv.status == I915_SAGV_ENABLED) return; drm_dbg_kms(&dev_priv->drm, "Enabling SAGV\n"); @@ -3759,14 +3759,14 @@ static void skl_sagv_enable(struct drm_i915_private *dev_priv) */ if (IS_SKYLAKE(dev_priv) && ret == -ENXIO) { drm_dbg(&dev_priv->drm, "No SAGV found on system, ignoring\n"); - dev_priv->sagv_status = I915_SAGV_NOT_CONTROLLED; + dev_priv->display.sagv.status = I915_SAGV_NOT_CONTROLLED; return; } else if (ret < 0) { drm_err(&dev_priv->drm, "Failed to enable SAGV\n"); return; } - dev_priv->sagv_status = I915_SAGV_ENABLED; + dev_priv->display.sagv.status = I915_SAGV_ENABLED; } static void skl_sagv_disable(struct drm_i915_private *dev_priv) @@ -3776,7 +3776,7 @@ static void skl_sagv_disable(struct drm_i915_private *dev_priv) if (!intel_has_sagv(dev_priv)) return; - if (dev_priv->sagv_status == I915_SAGV_DISABLED) + if (dev_priv->display.sagv.status == I915_SAGV_DISABLED) return; drm_dbg_kms(&dev_priv->drm, "Disabling SAGV\n"); @@ -3791,14 +3791,14 @@ static void skl_sagv_disable(struct drm_i915_private *dev_priv) */ if (IS_SKYLAKE(dev_priv) && ret == -ENXIO) { drm_dbg(&dev_priv->drm, "No SAGV found on system, ignoring\n"); - dev_priv->sagv_status = I915_SAGV_NOT_CONTROLLED; + dev_priv->display.sagv.status = I915_SAGV_NOT_CONTROLLED; return; } else if (ret < 0) { drm_err(&dev_priv->drm, "Failed to disable SAGV (%d)\n", ret); return; } - dev_priv->sagv_status = I915_SAGV_DISABLED; + dev_priv->display.sagv.status = I915_SAGV_DISABLED; } static void skl_sagv_pre_plane_update(struct intel_atomic_state *state) @@ -5560,8 +5560,8 @@ static void skl_compute_plane_wm(const struct intel_crtc_state *crtc_state, result->min_ddb_alloc = max(min_ddb_alloc, blocks) + 1; result->enable = true; - if (DISPLAY_VER(dev_priv) < 12 && dev_priv->sagv_block_time_us) - result->can_sagv = latency >= dev_priv->sagv_block_time_us; + if (DISPLAY_VER(dev_priv) < 12 && dev_priv->display.sagv.block_time_us) + result->can_sagv = latency >= dev_priv->display.sagv.block_time_us; } static void @@ -5595,8 +5595,8 @@ static void tgl_compute_sagv_wm(const struct intel_crtc_state *crtc_state, struct skl_wm_level *levels = plane_wm->wm; unsigned int latency = 0; - if (dev_priv->sagv_block_time_us) - latency = dev_priv->sagv_block_time_us + dev_priv->display.wm.skl_latency[0]; + if (dev_priv->display.sagv.block_time_us) + latency = dev_priv->display.sagv.block_time_us + dev_priv->display.wm.skl_latency[0]; skl_compute_plane_wm(crtc_state, plane, 0, latency, wm_params, &levels[0],

[19/39] drm/i915: move and group sagv under display.sagv

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