diff mbox series

[1/7] drm/i915/wm: move struct intel_watermark_params to i9xx_wm.c

Message ID d7408290c909eb67fc7a935469a3c6287b58587d.1724689818.git.jani.nikula@intel.com (mailing list archive)
State New
Headers show
Series drm/i915/display: intel_display_types.h cleanup | expand

Commit Message

Jani Nikula Aug. 26, 2024, 4:31 p.m. UTC
The definition is only used within i9xx_wm.c, hide it there.

Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
 drivers/gpu/drm/i915/display/i9xx_wm.c             | 8 ++++++++
 drivers/gpu/drm/i915/display/intel_display_types.h | 8 --------
 2 files changed, 8 insertions(+), 8 deletions(-)

Comments

Jani Nikula Sept. 5, 2024, 9:58 a.m. UTC | #1
On Thu, 05 Sep 2024, Luca Coelho <luca@coelho.fi> wrote:
> On Mon, 2024-08-26 at 19:31 +0300, Jani Nikula wrote:
>> The definition is only used within i9xx_wm.c, hide it there.
>> 
>> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
>> ---
>
> Reviewed-by: Luca Coelho <luciano.coelho@intel.com>

Thanks for the reviews, pushed the lot to drm-intel-next.

BR,
Jani.
diff mbox series

Patch

diff --git a/drivers/gpu/drm/i915/display/i9xx_wm.c b/drivers/gpu/drm/i915/display/i9xx_wm.c
index 15cda57fbc91..4e7ca5277bf1 100644
--- a/drivers/gpu/drm/i915/display/i9xx_wm.c
+++ b/drivers/gpu/drm/i915/display/i9xx_wm.c
@@ -14,6 +14,14 @@ 
 #include "skl_watermark.h"
 #include "vlv_sideband.h"
 
+struct intel_watermark_params {
+	u16 fifo_size;
+	u16 max_wm;
+	u8 default_wm;
+	u8 guard_size;
+	u8 cacheline_size;
+};
+
 /* used in computing the new watermarks state */
 struct intel_wm_config {
 	unsigned int num_pipes_active;
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
index bd290536a1b7..b4755fb8b94a 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -1601,14 +1601,6 @@  struct intel_plane {
 	void (*disable_flip_done)(struct intel_plane *plane);
 };
 
-struct intel_watermark_params {
-	u16 fifo_size;
-	u16 max_wm;
-	u8 default_wm;
-	u8 guard_size;
-	u8 cacheline_size;
-};
-
 #define to_intel_atomic_state(x) container_of(x, struct intel_atomic_state, base)
 #define to_intel_crtc(x) container_of(x, struct intel_crtc, base)
 #define to_intel_connector(x) container_of(x, struct intel_connector, base)