| Message ID | ec1aee8c7c0c8bce3e9d056fb90cc16135dd3be6.1662613377.git.ashutosh.dixit@intel.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | i915: freq caps and perf_limit_reasons changes for MTL | expand |
On Wed, Sep 07, 2022 at 10:23:57PM -0700, Ashutosh Dixit wrote: > For MTL, when reading from HW, RP0, RP1 (actuall RPe) and RPn freq use an > entirely different set of registers with different fields, bitwidths and > units. > > v2: Move MTL check into a separate function (Jani) > > Cc: Jani Nikula <jani.nikula@linux.intel.com> > Cc: Badal Nilawar <badal.nilawar@intel.com> > Signed-off-by: Ashutosh Dixit <ashutosh.dixit@intel.com> Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com> > --- > drivers/gpu/drm/i915/gt/intel_rps.c | 46 +++++++++++++++++++++++------ > drivers/gpu/drm/i915/i915_reg.h | 9 ++++++ > 2 files changed, 46 insertions(+), 9 deletions(-) > > diff --git a/drivers/gpu/drm/i915/gt/intel_rps.c b/drivers/gpu/drm/i915/gt/intel_rps.c > index 6fadde4ee7bf..234c69e2ca03 100644 > --- a/drivers/gpu/drm/i915/gt/intel_rps.c > +++ b/drivers/gpu/drm/i915/gt/intel_rps.c > @@ -1085,15 +1085,25 @@ static u32 intel_rps_read_state_cap(struct intel_rps *rps) > return intel_uncore_read(uncore, GEN6_RP_STATE_CAP); > } > > -/** > - * gen6_rps_get_freq_caps - Get freq caps exposed by HW > - * @rps: the intel_rps structure > - * @caps: returned freq caps > - * > - * Returned "caps" frequencies should be converted to MHz using > - * intel_gpu_freq() > - */ > -void gen6_rps_get_freq_caps(struct intel_rps *rps, struct intel_rps_freq_caps *caps) > +static void > +mtl_get_freq_caps(struct intel_rps *rps, struct intel_rps_freq_caps *caps) > +{ > + struct intel_uncore *uncore = rps_to_uncore(rps); > + u32 rp_state_cap = rps_to_gt(rps)->type == GT_MEDIA ? > + intel_uncore_read(uncore, MTL_MEDIAP_STATE_CAP) : > + intel_uncore_read(uncore, MTL_RP_STATE_CAP); > + u32 rpe = rps_to_gt(rps)->type == GT_MEDIA ? > + intel_uncore_read(uncore, MTL_MPE_FREQUENCY) : > + intel_uncore_read(uncore, MTL_GT_RPE_FREQUENCY); > + > + /* MTL values are in units of 16.67 MHz */ > + caps->rp0_freq = REG_FIELD_GET(MTL_RP0_CAP_MASK, rp_state_cap); > + caps->min_freq = REG_FIELD_GET(MTL_RPN_CAP_MASK, rp_state_cap); > + caps->rp1_freq = REG_FIELD_GET(MTL_RPE_MASK, rpe); > +} > + > +static void > +__gen6_rps_get_freq_caps(struct intel_rps *rps, struct intel_rps_freq_caps *caps) > { > struct drm_i915_private *i915 = rps_to_i915(rps); > u32 rp_state_cap; > @@ -1128,6 +1138,24 @@ void gen6_rps_get_freq_caps(struct intel_rps *rps, struct intel_rps_freq_caps *c > } > } > > +/** > + * gen6_rps_get_freq_caps - Get freq caps exposed by HW > + * @rps: the intel_rps structure > + * @caps: returned freq caps > + * > + * Returned "caps" frequencies should be converted to MHz using > + * intel_gpu_freq() > + */ > +void gen6_rps_get_freq_caps(struct intel_rps *rps, struct intel_rps_freq_caps *caps) > +{ > + struct drm_i915_private *i915 = rps_to_i915(rps); > + > + if (IS_METEORLAKE(i915)) > + return mtl_get_freq_caps(rps, caps); > + else > + return __gen6_rps_get_freq_caps(rps, caps); > +} > + > static void gen6_rps_init(struct intel_rps *rps) > { > struct drm_i915_private *i915 = rps_to_i915(rps); > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h > index 10a89d869b00..f008367a3433 100644 > --- a/drivers/gpu/drm/i915/i915_reg.h > +++ b/drivers/gpu/drm/i915/i915_reg.h > @@ -1792,6 +1792,15 @@ > #define XEHPSDV_RP_STATE_CAP _MMIO(0x250014) > #define PVC_RP_STATE_CAP _MMIO(0x281014) > > +#define MTL_RP_STATE_CAP _MMIO(0x138000) > +#define MTL_MEDIAP_STATE_CAP _MMIO(0x138020) > +#define MTL_RP0_CAP_MASK REG_GENMASK(8, 0) > +#define MTL_RPN_CAP_MASK REG_GENMASK(24, 16) > + > +#define MTL_GT_RPE_FREQUENCY _MMIO(0x13800c) > +#define MTL_MPE_FREQUENCY _MMIO(0x13802c) > +#define MTL_RPE_MASK REG_GENMASK(8, 0) > + > #define GT0_PERF_LIMIT_REASONS _MMIO(0x1381a8) > #define GT0_PERF_LIMIT_REASONS_MASK 0xde3 > #define PROCHOT_MASK REG_BIT(0) > -- > 2.34.1 >
diff --git a/drivers/gpu/drm/i915/gt/intel_rps.c b/drivers/gpu/drm/i915/gt/intel_rps.c index 6fadde4ee7bf..234c69e2ca03 100644 --- a/drivers/gpu/drm/i915/gt/intel_rps.c +++ b/drivers/gpu/drm/i915/gt/intel_rps.c @@ -1085,15 +1085,25 @@ static u32 intel_rps_read_state_cap(struct intel_rps *rps) return intel_uncore_read(uncore, GEN6_RP_STATE_CAP); } -/** - * gen6_rps_get_freq_caps - Get freq caps exposed by HW - * @rps: the intel_rps structure - * @caps: returned freq caps - * - * Returned "caps" frequencies should be converted to MHz using - * intel_gpu_freq() - */ -void gen6_rps_get_freq_caps(struct intel_rps *rps, struct intel_rps_freq_caps *caps) +static void +mtl_get_freq_caps(struct intel_rps *rps, struct intel_rps_freq_caps *caps) +{ + struct intel_uncore *uncore = rps_to_uncore(rps); + u32 rp_state_cap = rps_to_gt(rps)->type == GT_MEDIA ? + intel_uncore_read(uncore, MTL_MEDIAP_STATE_CAP) : + intel_uncore_read(uncore, MTL_RP_STATE_CAP); + u32 rpe = rps_to_gt(rps)->type == GT_MEDIA ? + intel_uncore_read(uncore, MTL_MPE_FREQUENCY) : + intel_uncore_read(uncore, MTL_GT_RPE_FREQUENCY); + + /* MTL values are in units of 16.67 MHz */ + caps->rp0_freq = REG_FIELD_GET(MTL_RP0_CAP_MASK, rp_state_cap); + caps->min_freq = REG_FIELD_GET(MTL_RPN_CAP_MASK, rp_state_cap); + caps->rp1_freq = REG_FIELD_GET(MTL_RPE_MASK, rpe); +} + +static void +__gen6_rps_get_freq_caps(struct intel_rps *rps, struct intel_rps_freq_caps *caps) { struct drm_i915_private *i915 = rps_to_i915(rps); u32 rp_state_cap; @@ -1128,6 +1138,24 @@ void gen6_rps_get_freq_caps(struct intel_rps *rps, struct intel_rps_freq_caps *c } } +/** + * gen6_rps_get_freq_caps - Get freq caps exposed by HW + * @rps: the intel_rps structure + * @caps: returned freq caps + * + * Returned "caps" frequencies should be converted to MHz using + * intel_gpu_freq() + */ +void gen6_rps_get_freq_caps(struct intel_rps *rps, struct intel_rps_freq_caps *caps) +{ + struct drm_i915_private *i915 = rps_to_i915(rps); + + if (IS_METEORLAKE(i915)) + return mtl_get_freq_caps(rps, caps); + else + return __gen6_rps_get_freq_caps(rps, caps); +} + static void gen6_rps_init(struct intel_rps *rps) { struct drm_i915_private *i915 = rps_to_i915(rps); diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 10a89d869b00..f008367a3433 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -1792,6 +1792,15 @@ #define XEHPSDV_RP_STATE_CAP _MMIO(0x250014) #define PVC_RP_STATE_CAP _MMIO(0x281014) +#define MTL_RP_STATE_CAP _MMIO(0x138000) +#define MTL_MEDIAP_STATE_CAP _MMIO(0x138020) +#define MTL_RP0_CAP_MASK REG_GENMASK(8, 0) +#define MTL_RPN_CAP_MASK REG_GENMASK(24, 16) + +#define MTL_GT_RPE_FREQUENCY _MMIO(0x13800c) +#define MTL_MPE_FREQUENCY _MMIO(0x13802c) +#define MTL_RPE_MASK REG_GENMASK(8, 0) + #define GT0_PERF_LIMIT_REASONS _MMIO(0x1381a8) #define GT0_PERF_LIMIT_REASONS_MASK 0xde3 #define PROCHOT_MASK REG_BIT(0)
For MTL, when reading from HW, RP0, RP1 (actuall RPe) and RPn freq use an entirely different set of registers with different fields, bitwidths and units. v2: Move MTL check into a separate function (Jani) Cc: Jani Nikula <jani.nikula@linux.intel.com> Cc: Badal Nilawar <badal.nilawar@intel.com> Signed-off-by: Ashutosh Dixit <ashutosh.dixit@intel.com> --- drivers/gpu/drm/i915/gt/intel_rps.c | 46 +++++++++++++++++++++++------ drivers/gpu/drm/i915/i915_reg.h | 9 ++++++ 2 files changed, 46 insertions(+), 9 deletions(-)