| Message ID | eed742e2de036d4050308fa064a92060a5736b45.1583340549.git.caz.yokoyama@intel.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | [1/1] Revert "drm/i915/tgl: Add extra hdc flush workaround" | expand |
On Wed, Mar 04, 2020 at 08:52:25AM -0800, Caz Yokoyama wrote: > This reverts commit 36a6b5d964d995b536b1925ec42052ee40ba92c4. > > The commit takes care Wa_1604544889 which was fixed on a0 stepping based on > a0 replan. So no SW workaround is required on any stepping now. > > Signed-off-by: Caz Yokoyama <caz.yokoyama@intel.com> Matches what I see in the bspec and WA database. Reviewed-by: Matt Roper <matthew.d.roper@intel.com> I believe the maintainers prefer that we also add Fixes: notation for reverts now, so Fixes: 36a6b5d964d9 ("drm/i915/tgl: Add extra hdc flush workaround") too. Matt > --- > drivers/gpu/drm/i915/gt/intel_lrc.c | 20 -------------------- > 1 file changed, 20 deletions(-) > > diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c b/drivers/gpu/drm/i915/gt/intel_lrc.c > index b9b3f78f1324..f9425e5ed7ea 100644 > --- a/drivers/gpu/drm/i915/gt/intel_lrc.c > +++ b/drivers/gpu/drm/i915/gt/intel_lrc.c > @@ -4145,26 +4145,6 @@ static int gen12_emit_flush_render(struct i915_request *request, > > *cs++ = preparser_disable(false); > intel_ring_advance(request, cs); > - > - /* > - * Wa_1604544889:tgl > - */ > - if (IS_TGL_REVID(request->i915, TGL_REVID_A0, TGL_REVID_A0)) { > - flags = 0; > - flags |= PIPE_CONTROL_CS_STALL; > - flags |= PIPE_CONTROL_HDC_PIPELINE_FLUSH; > - > - flags |= PIPE_CONTROL_STORE_DATA_INDEX; > - flags |= PIPE_CONTROL_QW_WRITE; > - > - cs = intel_ring_begin(request, 6); > - if (IS_ERR(cs)) > - return PTR_ERR(cs); > - > - cs = gen8_emit_pipe_control(cs, flags, > - LRC_PPHWSP_SCRATCH_ADDR); > - intel_ring_advance(request, cs); > - } > } > > return 0; > -- > 2.21.0.5.gaeb582a983 >
diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c b/drivers/gpu/drm/i915/gt/intel_lrc.c index b9b3f78f1324..f9425e5ed7ea 100644 --- a/drivers/gpu/drm/i915/gt/intel_lrc.c +++ b/drivers/gpu/drm/i915/gt/intel_lrc.c @@ -4145,26 +4145,6 @@ static int gen12_emit_flush_render(struct i915_request *request, *cs++ = preparser_disable(false); intel_ring_advance(request, cs); - - /* - * Wa_1604544889:tgl - */ - if (IS_TGL_REVID(request->i915, TGL_REVID_A0, TGL_REVID_A0)) { - flags = 0; - flags |= PIPE_CONTROL_CS_STALL; - flags |= PIPE_CONTROL_HDC_PIPELINE_FLUSH; - - flags |= PIPE_CONTROL_STORE_DATA_INDEX; - flags |= PIPE_CONTROL_QW_WRITE; - - cs = intel_ring_begin(request, 6); - if (IS_ERR(cs)) - return PTR_ERR(cs); - - cs = gen8_emit_pipe_control(cs, flags, - LRC_PPHWSP_SCRATCH_ADDR); - intel_ring_advance(request, cs); - } } return 0;
This reverts commit 36a6b5d964d995b536b1925ec42052ee40ba92c4. The commit takes care Wa_1604544889 which was fixed on a0 stepping based on a0 replan. So no SW workaround is required on any stepping now. Signed-off-by: Caz Yokoyama <caz.yokoyama@intel.com> --- drivers/gpu/drm/i915/gt/intel_lrc.c | 20 -------------------- 1 file changed, 20 deletions(-)