diff mbox

[3/7] drm/i915/vlv: use per-pipe backlight controls v2

Message ID f5684e0c49925254753990c65d1fdbadc76ec212.1383237868.git.jani.nikula@intel.com (mailing list archive)
State New, archived
Headers show

Commit Message

Jani Nikula Oct. 31, 2013, 4:55 p.m. UTC 
From: Jesse Barnes <jbarnes@virtuousgeek.org>

With the connector and pipe passed around, we can now set the backlight
on the right pipe on VLV/BYT.

v2: drop combination mode check for VLV (Jani)
    add save/restore code for VLV backlight regs (Jani)
    check for existing modulation freq when initializing backlight regs (Jani)

Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
 drivers/gpu/drm/i915/i915_drv.h     |    3 ++
 drivers/gpu/drm/i915/i915_reg.h     |   15 ++++++++
 drivers/gpu/drm/i915/i915_suspend.c |   29 +++++++++++++++
 drivers/gpu/drm/i915/intel_panel.c  |   67 ++++++++++++++++++++++++++++-------
 4 files changed, 102 insertions(+), 12 deletions(-)

Comments

Joe Konno Nov. 6, 2013, 5:09 p.m. UTC | #1 
On 10/31/2013 09:55 AM, Jani Nikula wrote:
> From: Jesse Barnes <jbarnes@virtuousgeek.org>
>
> With the connector and pipe passed around, we can now set the backlight
> on the right pipe on VLV/BYT.
>
> v2: drop combination mode check for VLV (Jani)
>      add save/restore code for VLV backlight regs (Jani)
>      check for existing modulation freq when initializing backlight regs (Jani)
>
> Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
> ---
>   drivers/gpu/drm/i915/i915_drv.h     |    3 ++
>   drivers/gpu/drm/i915/i915_reg.h     |   15 ++++++++
>   drivers/gpu/drm/i915/i915_suspend.c |   29 +++++++++++++++
>   drivers/gpu/drm/i915/intel_panel.c  |   67 ++++++++++++++++++++++++++++-------
>   4 files changed, 102 insertions(+), 12 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index 83eda64..16fae30 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -745,6 +745,9 @@ struct i915_suspend_saved_registers {
>   	u32 saveBLC_HIST_CTL;
>   	u32 saveBLC_PWM_CTL;
>   	u32 saveBLC_PWM_CTL2;
> +	u32 saveBLC_HIST_CTL_B;
> +	u32 saveBLC_PWM_CTL_B;
> +	u32 saveBLC_PWM_CTL2_B;
>   	u32 saveBLC_CPU_PWM_CTL;
>   	u32 saveBLC_CPU_PWM_CTL2;
>   	u32 saveFPB0;
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 4d2db59..e2f3dd4 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -2387,6 +2387,21 @@
>
>   #define PFIT_AUTO_RATIOS (dev_priv->info->display_mmio_offset + 0x61238)
>
> +#define _VLV_BLC_PWM_CTL2_A (dev_priv->info->display_mmio_offset + 0x61250)
> +#define _VLV_BLC_PWM_CTL2_B (dev_priv->info->display_mmio_offset + 0x61350)
> +#define VLV_BLC_PWM_CTL2(pipe) _PIPE(pipe, _VLV_BLC_PWM_CTL2_A, \
> +				     _VLV_BLC_PWM_CTL2_B)
> +
> +#define _VLV_BLC_PWM_CTL_A (dev_priv->info->display_mmio_offset + 0x61254)
> +#define _VLV_BLC_PWM_CTL_B (dev_priv->info->display_mmio_offset + 0x61354)
> +#define VLV_BLC_PWM_CTL(pipe) _PIPE(pipe, _VLV_BLC_PWM_CTL_A, \
> +				    _VLV_BLC_PWM_CTL_B)
> +
> +#define _VLV_BLC_HIST_CTL_A (dev_priv->info->display_mmio_offset + 0x61260)
> +#define _VLV_BLC_HIST_CTL_B (dev_priv->info->display_mmio_offset + 0x61360)
> +#define VLV_BLC_HIST_CTL(pipe) _PIPE(pipe, _VLV_BLC_HIST_CTL_A, \
> +				     _VLV_BLC_HIST_CTL_B)
> +
>   /* Backlight control */
>   #define BLC_PWM_CTL2	(dev_priv->info->display_mmio_offset + 0x61250) /* 965+ only */
>   #define   BLM_PWM_ENABLE		(1 << 31)
> diff --git a/drivers/gpu/drm/i915/i915_suspend.c b/drivers/gpu/drm/i915/i915_suspend.c
> index a088f1f..98790c7 100644
> --- a/drivers/gpu/drm/i915/i915_suspend.c
> +++ b/drivers/gpu/drm/i915/i915_suspend.c
> @@ -214,6 +214,22 @@ static void i915_save_display(struct drm_device *dev)
>   		dev_priv->regfile.saveBLC_CPU_PWM_CTL2 = I915_READ(BLC_PWM_CPU_CTL2);
>   		if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
>   			dev_priv->regfile.saveLVDS = I915_READ(PCH_LVDS);
> +	} else if (IS_VALLEYVIEW(dev)) {
> +		dev_priv->regfile.savePP_CONTROL = I915_READ(PP_CONTROL);
> +		dev_priv->regfile.savePFIT_PGM_RATIOS = I915_READ(PFIT_PGM_RATIOS);
> +
> +		dev_priv->regfile.saveBLC_PWM_CTL =
> +			I915_READ(VLV_BLC_PWM_CTL(PIPE_A));
> +		dev_priv->regfile.saveBLC_HIST_CTL =
> +			I915_READ(VLV_BLC_HIST_CTL(PIPE_A));
> +		dev_priv->regfile.saveBLC_PWM_CTL2 =
> +			I915_READ(VLV_BLC_PWM_CTL2(PIPE_A));
> +		dev_priv->regfile.saveBLC_PWM_CTL_B =
> +			I915_READ(VLV_BLC_PWM_CTL(PIPE_B));
> +		dev_priv->regfile.saveBLC_HIST_CTL_B =
> +			I915_READ(VLV_BLC_HIST_CTL(PIPE_B));
> +		dev_priv->regfile.saveBLC_PWM_CTL2_B =
> +			I915_READ(VLV_BLC_PWM_CTL2(PIPE_B));
>   	} else {
>   		dev_priv->regfile.savePP_CONTROL = I915_READ(PP_CONTROL);
>   		dev_priv->regfile.savePFIT_PGM_RATIOS = I915_READ(PFIT_PGM_RATIOS);
> @@ -302,6 +318,19 @@ static void i915_restore_display(struct drm_device *dev)
>   		I915_WRITE(PCH_PP_CONTROL, dev_priv->regfile.savePP_CONTROL);
>   		I915_WRITE(RSTDBYCTL,
>   			   dev_priv->regfile.saveMCHBAR_RENDER_STANDBY);
> +	} else if (IS_VALLEYVIEW(dev)) {
> +		I915_WRITE(VLV_BLC_PWM_CTL(PIPE_A),
> +			   dev_priv->regfile.saveBLC_PWM_CTL);
> +		I915_WRITE(VLV_BLC_HIST_CTL(PIPE_A),
> +			   dev_priv->regfile.saveBLC_HIST_CTL);
> +		I915_WRITE(VLV_BLC_PWM_CTL2(PIPE_A),
> +			   dev_priv->regfile.saveBLC_PWM_CTL2);
> +		I915_WRITE(VLV_BLC_PWM_CTL(PIPE_B),
> +			   dev_priv->regfile.saveBLC_PWM_CTL);
> +		I915_WRITE(VLV_BLC_HIST_CTL(PIPE_B),
> +			   dev_priv->regfile.saveBLC_HIST_CTL);
> +		I915_WRITE(VLV_BLC_PWM_CTL2(PIPE_B),
> +			   dev_priv->regfile.saveBLC_PWM_CTL2);
>   	} else {
>   		I915_WRITE(PFIT_PGM_RATIOS, dev_priv->regfile.savePFIT_PGM_RATIOS);
>   		I915_WRITE(BLC_PWM_CTL, dev_priv->regfile.saveBLC_PWM_CTL);
> diff --git a/drivers/gpu/drm/i915/intel_panel.c b/drivers/gpu/drm/i915/intel_panel.c
> index 0f1ebc8..f161ac0 100644
> --- a/drivers/gpu/drm/i915/intel_panel.c
> +++ b/drivers/gpu/drm/i915/intel_panel.c
> @@ -358,6 +358,21 @@ static u32 i915_read_blc_pwm_ctl(struct drm_device *dev, enum pipe pipe)
>   			val = dev_priv->regfile.saveBLC_PWM_CTL2;
>   			I915_WRITE(BLC_PWM_PCH_CTL2, val);
>   		}
> +	} else if (IS_VALLEYVIEW(dev)) {
> +		val = I915_READ(VLV_BLC_PWM_CTL(pipe));
> +		if (dev_priv->regfile.saveBLC_PWM_CTL == 0) {
> +			dev_priv->regfile.saveBLC_PWM_CTL = val;
> +			dev_priv->regfile.saveBLC_PWM_CTL2 =
> +				I915_READ(VLV_BLC_PWM_CTL2(pipe));
> +		} else if (val == 0) {
> +			val = dev_priv->regfile.saveBLC_PWM_CTL;
> +			I915_WRITE(VLV_BLC_PWM_CTL(pipe), val);
> +			I915_WRITE(VLV_BLC_PWM_CTL2(pipe),
> +				   dev_priv->regfile.saveBLC_PWM_CTL2);
> +		}
> +
> +		if (!val)
> +			val = 0x0f42ffff;
>   	} else {
>   		val = I915_READ(BLC_PWM_CTL);
>   		if (dev_priv->regfile.saveBLC_PWM_CTL == 0) {
> @@ -372,9 +387,6 @@ static u32 i915_read_blc_pwm_ctl(struct drm_device *dev, enum pipe pipe)
>   				I915_WRITE(BLC_PWM_CTL2,
>   					   dev_priv->regfile.saveBLC_PWM_CTL2);
>   		}
> -
> -		if (IS_VALLEYVIEW(dev) && !val)
> -			val = 0x0f42ffff;
>   	}
>
>   	return val;
> @@ -435,13 +447,19 @@ static u32 intel_panel_get_backlight(struct drm_device *dev,
>   	struct drm_i915_private *dev_priv = dev->dev_private;
>   	u32 val;
>   	unsigned long flags;
> +	int reg;
>
>   	spin_lock_irqsave(&dev_priv->backlight.lock, flags);
>
>   	if (HAS_PCH_SPLIT(dev)) {
>   		val = I915_READ(BLC_PWM_CPU_CTL) & BACKLIGHT_DUTY_CYCLE_MASK;
>   	} else {
> -		val = I915_READ(BLC_PWM_CTL) & BACKLIGHT_DUTY_CYCLE_MASK;
> +		if (IS_VALLEYVIEW(dev))
> +			reg = VLV_BLC_PWM_CTL(pipe);
> +		else
> +			reg = BLC_PWM_CTL;
> +
> +		val = I915_READ(reg) & BACKLIGHT_DUTY_CYCLE_MASK;
>   		if (INTEL_INFO(dev)->gen < 4)
>   			val >>= 1;
>
> @@ -473,6 +491,7 @@ static void intel_panel_actually_set_backlight(struct drm_device *dev,
>   {
>   	struct drm_i915_private *dev_priv = dev->dev_private;
>   	u32 tmp;
> +	int reg;
>
>   	DRM_DEBUG_DRIVER("set backlight PWM = %d\n", level);
>   	level = intel_panel_compute_brightness(dev, pipe, level);
> @@ -493,11 +512,16 @@ static void intel_panel_actually_set_backlight(struct drm_device *dev,
>   		pci_write_config_byte(dev->pdev, PCI_LBPC, lbpc);
>   	}
>
> -	tmp = I915_READ(BLC_PWM_CTL);
> +	if (IS_VALLEYVIEW(dev))
> +		reg = VLV_BLC_PWM_CTL(pipe);
> +	else
> +		reg = BLC_PWM_CTL;
> +
> +	tmp = I915_READ(reg);
>   	if (INTEL_INFO(dev)->gen < 4)
>   		level <<= 1;
>   	tmp &= ~BACKLIGHT_DUTY_CYCLE_MASK;
> -	I915_WRITE(BLC_PWM_CTL, tmp | level);
> +	I915_WRITE(reg, tmp | level);
>   }
>
>   /* set backlight brightness to level in range [0..max] */
> @@ -566,7 +590,12 @@ void intel_panel_disable_backlight(struct intel_connector *connector)
>   	if (INTEL_INFO(dev)->gen >= 4) {
>   		uint32_t reg, tmp;
>
> -		reg = HAS_PCH_SPLIT(dev) ? BLC_PWM_CPU_CTL2 : BLC_PWM_CTL2;
> +		if (HAS_PCH_SPLIT(dev))
> +			reg = BLC_PWM_CPU_CTL2;
> +		else if (IS_VALLEYVIEW(dev))
> +			reg = VLV_BLC_PWM_CTL2(pipe);
> +		else
> +			reg = BLC_PWM_CTL2;
>
>   		I915_WRITE(reg, I915_READ(reg) & ~BLM_PWM_ENABLE);
>
> @@ -607,8 +636,12 @@ void intel_panel_enable_backlight(struct intel_connector *connector)
>   	if (INTEL_INFO(dev)->gen >= 4) {
>   		uint32_t reg, tmp;
>
> -		reg = HAS_PCH_SPLIT(dev) ? BLC_PWM_CPU_CTL2 : BLC_PWM_CTL2;
> -
> +		if (HAS_PCH_SPLIT(dev))
> +			reg = BLC_PWM_CPU_CTL2;
> +		else if (IS_VALLEYVIEW(dev))
> +			reg = VLV_BLC_PWM_CTL2(pipe);
> +		else
> +			reg = BLC_PWM_CTL2;
>
>   		tmp = I915_READ(reg);
>
> @@ -660,9 +693,19 @@ static void intel_panel_init_backlight_regs(struct drm_device *dev)
>   	struct drm_i915_private *dev_priv = dev->dev_private;
>
>   	if (IS_VALLEYVIEW(dev)) {
> -		u32 cur_val = I915_READ(BLC_PWM_CTL) &
> -			BACKLIGHT_DUTY_CYCLE_MASK;
> -		I915_WRITE(BLC_PWM_CTL, (0xf42 << 16) | cur_val);
> +		enum pipe pipe;
> +
> +		for_each_pipe(pipe) {
> +			u32 cur_val = I915_READ(VLV_BLC_PWM_CTL(pipe));
> +
> +			/* Skip if the modulation freq is already set */
> +			if (cur_val & ~BACKLIGHT_DUTY_CYCLE_MASK)
> +				continue;
> +
> +			cur_val &= BACKLIGHT_DUTY_CYCLE_MASK;
> +			I915_WRITE(VLV_BLC_PWM_CTL(pipe), (0xf42 << 16) |
> +				   cur_val);
> +		}
>   	}
>   }
>
>

Tested-by: Joe Konno <joe.konno@intel.com>
diff mbox

Patch

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 83eda64..16fae30 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -745,6 +745,9 @@  struct i915_suspend_saved_registers {
 	u32 saveBLC_HIST_CTL;
 	u32 saveBLC_PWM_CTL;
 	u32 saveBLC_PWM_CTL2;
+	u32 saveBLC_HIST_CTL_B;
+	u32 saveBLC_PWM_CTL_B;
+	u32 saveBLC_PWM_CTL2_B;
 	u32 saveBLC_CPU_PWM_CTL;
 	u32 saveBLC_CPU_PWM_CTL2;
 	u32 saveFPB0;
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 4d2db59..e2f3dd4 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -2387,6 +2387,21 @@ 
 
 #define PFIT_AUTO_RATIOS (dev_priv->info->display_mmio_offset + 0x61238)
 
+#define _VLV_BLC_PWM_CTL2_A (dev_priv->info->display_mmio_offset + 0x61250)
+#define _VLV_BLC_PWM_CTL2_B (dev_priv->info->display_mmio_offset + 0x61350)
+#define VLV_BLC_PWM_CTL2(pipe) _PIPE(pipe, _VLV_BLC_PWM_CTL2_A, \
+				     _VLV_BLC_PWM_CTL2_B)
+
+#define _VLV_BLC_PWM_CTL_A (dev_priv->info->display_mmio_offset + 0x61254)
+#define _VLV_BLC_PWM_CTL_B (dev_priv->info->display_mmio_offset + 0x61354)
+#define VLV_BLC_PWM_CTL(pipe) _PIPE(pipe, _VLV_BLC_PWM_CTL_A, \
+				    _VLV_BLC_PWM_CTL_B)
+
+#define _VLV_BLC_HIST_CTL_A (dev_priv->info->display_mmio_offset + 0x61260)
+#define _VLV_BLC_HIST_CTL_B (dev_priv->info->display_mmio_offset + 0x61360)
+#define VLV_BLC_HIST_CTL(pipe) _PIPE(pipe, _VLV_BLC_HIST_CTL_A, \
+				     _VLV_BLC_HIST_CTL_B)
+
 /* Backlight control */
 #define BLC_PWM_CTL2	(dev_priv->info->display_mmio_offset + 0x61250) /* 965+ only */
 #define   BLM_PWM_ENABLE		(1 << 31)
diff --git a/drivers/gpu/drm/i915/i915_suspend.c b/drivers/gpu/drm/i915/i915_suspend.c
index a088f1f..98790c7 100644
--- a/drivers/gpu/drm/i915/i915_suspend.c
+++ b/drivers/gpu/drm/i915/i915_suspend.c
@@ -214,6 +214,22 @@  static void i915_save_display(struct drm_device *dev)
 		dev_priv->regfile.saveBLC_CPU_PWM_CTL2 = I915_READ(BLC_PWM_CPU_CTL2);
 		if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
 			dev_priv->regfile.saveLVDS = I915_READ(PCH_LVDS);
+	} else if (IS_VALLEYVIEW(dev)) {
+		dev_priv->regfile.savePP_CONTROL = I915_READ(PP_CONTROL);
+		dev_priv->regfile.savePFIT_PGM_RATIOS = I915_READ(PFIT_PGM_RATIOS);
+
+		dev_priv->regfile.saveBLC_PWM_CTL =
+			I915_READ(VLV_BLC_PWM_CTL(PIPE_A));
+		dev_priv->regfile.saveBLC_HIST_CTL =
+			I915_READ(VLV_BLC_HIST_CTL(PIPE_A));
+		dev_priv->regfile.saveBLC_PWM_CTL2 =
+			I915_READ(VLV_BLC_PWM_CTL2(PIPE_A));
+		dev_priv->regfile.saveBLC_PWM_CTL_B =
+			I915_READ(VLV_BLC_PWM_CTL(PIPE_B));
+		dev_priv->regfile.saveBLC_HIST_CTL_B =
+			I915_READ(VLV_BLC_HIST_CTL(PIPE_B));
+		dev_priv->regfile.saveBLC_PWM_CTL2_B =
+			I915_READ(VLV_BLC_PWM_CTL2(PIPE_B));
 	} else {
 		dev_priv->regfile.savePP_CONTROL = I915_READ(PP_CONTROL);
 		dev_priv->regfile.savePFIT_PGM_RATIOS = I915_READ(PFIT_PGM_RATIOS);
@@ -302,6 +318,19 @@  static void i915_restore_display(struct drm_device *dev)
 		I915_WRITE(PCH_PP_CONTROL, dev_priv->regfile.savePP_CONTROL);
 		I915_WRITE(RSTDBYCTL,
 			   dev_priv->regfile.saveMCHBAR_RENDER_STANDBY);
+	} else if (IS_VALLEYVIEW(dev)) {
+		I915_WRITE(VLV_BLC_PWM_CTL(PIPE_A),
+			   dev_priv->regfile.saveBLC_PWM_CTL);
+		I915_WRITE(VLV_BLC_HIST_CTL(PIPE_A),
+			   dev_priv->regfile.saveBLC_HIST_CTL);
+		I915_WRITE(VLV_BLC_PWM_CTL2(PIPE_A),
+			   dev_priv->regfile.saveBLC_PWM_CTL2);
+		I915_WRITE(VLV_BLC_PWM_CTL(PIPE_B),
+			   dev_priv->regfile.saveBLC_PWM_CTL);
+		I915_WRITE(VLV_BLC_HIST_CTL(PIPE_B),
+			   dev_priv->regfile.saveBLC_HIST_CTL);
+		I915_WRITE(VLV_BLC_PWM_CTL2(PIPE_B),
+			   dev_priv->regfile.saveBLC_PWM_CTL2);
 	} else {
 		I915_WRITE(PFIT_PGM_RATIOS, dev_priv->regfile.savePFIT_PGM_RATIOS);
 		I915_WRITE(BLC_PWM_CTL, dev_priv->regfile.saveBLC_PWM_CTL);
diff --git a/drivers/gpu/drm/i915/intel_panel.c b/drivers/gpu/drm/i915/intel_panel.c
index 0f1ebc8..f161ac0 100644
--- a/drivers/gpu/drm/i915/intel_panel.c
+++ b/drivers/gpu/drm/i915/intel_panel.c
@@ -358,6 +358,21 @@  static u32 i915_read_blc_pwm_ctl(struct drm_device *dev, enum pipe pipe)
 			val = dev_priv->regfile.saveBLC_PWM_CTL2;
 			I915_WRITE(BLC_PWM_PCH_CTL2, val);
 		}
+	} else if (IS_VALLEYVIEW(dev)) {
+		val = I915_READ(VLV_BLC_PWM_CTL(pipe));
+		if (dev_priv->regfile.saveBLC_PWM_CTL == 0) {
+			dev_priv->regfile.saveBLC_PWM_CTL = val;
+			dev_priv->regfile.saveBLC_PWM_CTL2 =
+				I915_READ(VLV_BLC_PWM_CTL2(pipe));
+		} else if (val == 0) {
+			val = dev_priv->regfile.saveBLC_PWM_CTL;
+			I915_WRITE(VLV_BLC_PWM_CTL(pipe), val);
+			I915_WRITE(VLV_BLC_PWM_CTL2(pipe),
+				   dev_priv->regfile.saveBLC_PWM_CTL2);
+		}
+
+		if (!val)
+			val = 0x0f42ffff;
 	} else {
 		val = I915_READ(BLC_PWM_CTL);
 		if (dev_priv->regfile.saveBLC_PWM_CTL == 0) {
@@ -372,9 +387,6 @@  static u32 i915_read_blc_pwm_ctl(struct drm_device *dev, enum pipe pipe)
 				I915_WRITE(BLC_PWM_CTL2,
 					   dev_priv->regfile.saveBLC_PWM_CTL2);
 		}
-
-		if (IS_VALLEYVIEW(dev) && !val)
-			val = 0x0f42ffff;
 	}
 
 	return val;
@@ -435,13 +447,19 @@  static u32 intel_panel_get_backlight(struct drm_device *dev,
 	struct drm_i915_private *dev_priv = dev->dev_private;
 	u32 val;
 	unsigned long flags;
+	int reg;
 
 	spin_lock_irqsave(&dev_priv->backlight.lock, flags);
 
 	if (HAS_PCH_SPLIT(dev)) {
 		val = I915_READ(BLC_PWM_CPU_CTL) & BACKLIGHT_DUTY_CYCLE_MASK;
 	} else {
-		val = I915_READ(BLC_PWM_CTL) & BACKLIGHT_DUTY_CYCLE_MASK;
+		if (IS_VALLEYVIEW(dev))
+			reg = VLV_BLC_PWM_CTL(pipe);
+		else
+			reg = BLC_PWM_CTL;
+
+		val = I915_READ(reg) & BACKLIGHT_DUTY_CYCLE_MASK;
 		if (INTEL_INFO(dev)->gen < 4)
 			val >>= 1;
 
@@ -473,6 +491,7 @@  static void intel_panel_actually_set_backlight(struct drm_device *dev,
 {
 	struct drm_i915_private *dev_priv = dev->dev_private;
 	u32 tmp;
+	int reg;
 
 	DRM_DEBUG_DRIVER("set backlight PWM = %d\n", level);
 	level = intel_panel_compute_brightness(dev, pipe, level);
@@ -493,11 +512,16 @@  static void intel_panel_actually_set_backlight(struct drm_device *dev,
 		pci_write_config_byte(dev->pdev, PCI_LBPC, lbpc);
 	}
 
-	tmp = I915_READ(BLC_PWM_CTL);
+	if (IS_VALLEYVIEW(dev))
+		reg = VLV_BLC_PWM_CTL(pipe);
+	else
+		reg = BLC_PWM_CTL;
+
+	tmp = I915_READ(reg);
 	if (INTEL_INFO(dev)->gen < 4)
 		level <<= 1;
 	tmp &= ~BACKLIGHT_DUTY_CYCLE_MASK;
-	I915_WRITE(BLC_PWM_CTL, tmp | level);
+	I915_WRITE(reg, tmp | level);
 }
 
 /* set backlight brightness to level in range [0..max] */
@@ -566,7 +590,12 @@  void intel_panel_disable_backlight(struct intel_connector *connector)
 	if (INTEL_INFO(dev)->gen >= 4) {
 		uint32_t reg, tmp;
 
-		reg = HAS_PCH_SPLIT(dev) ? BLC_PWM_CPU_CTL2 : BLC_PWM_CTL2;
+		if (HAS_PCH_SPLIT(dev))
+			reg = BLC_PWM_CPU_CTL2;
+		else if (IS_VALLEYVIEW(dev))
+			reg = VLV_BLC_PWM_CTL2(pipe);
+		else
+			reg = BLC_PWM_CTL2;
 
 		I915_WRITE(reg, I915_READ(reg) & ~BLM_PWM_ENABLE);
 
@@ -607,8 +636,12 @@  void intel_panel_enable_backlight(struct intel_connector *connector)
 	if (INTEL_INFO(dev)->gen >= 4) {
 		uint32_t reg, tmp;
 
-		reg = HAS_PCH_SPLIT(dev) ? BLC_PWM_CPU_CTL2 : BLC_PWM_CTL2;
-
+		if (HAS_PCH_SPLIT(dev))
+			reg = BLC_PWM_CPU_CTL2;
+		else if (IS_VALLEYVIEW(dev))
+			reg = VLV_BLC_PWM_CTL2(pipe);
+		else
+			reg = BLC_PWM_CTL2;
 
 		tmp = I915_READ(reg);
 
@@ -660,9 +693,19 @@  static void intel_panel_init_backlight_regs(struct drm_device *dev)
 	struct drm_i915_private *dev_priv = dev->dev_private;
 
 	if (IS_VALLEYVIEW(dev)) {
-		u32 cur_val = I915_READ(BLC_PWM_CTL) &
-			BACKLIGHT_DUTY_CYCLE_MASK;
-		I915_WRITE(BLC_PWM_CTL, (0xf42 << 16) | cur_val);
+		enum pipe pipe;
+
+		for_each_pipe(pipe) {
+			u32 cur_val = I915_READ(VLV_BLC_PWM_CTL(pipe));
+
+			/* Skip if the modulation freq is already set */
+			if (cur_val & ~BACKLIGHT_DUTY_CYCLE_MASK)
+				continue;
+
+			cur_val &= BACKLIGHT_DUTY_CYCLE_MASK;
+			I915_WRITE(VLV_BLC_PWM_CTL(pipe), (0xf42 << 16) |
+				   cur_val);
+		}
 	}
 }