| Message ID | f56e48a927692cec382e292602e0fa68e37f3b93.1725974820.git.jani.nikula@intel.com (mailing list archive) |
|---|---|
| State | New |
| Headers | show |
| Series | drm/i915: register style fixes | expand |
On Tue, Sep 10, 2024 at 04:28:50PM +0300, Jani Nikula wrote: > Adhere to the style described at the top of i915_reg.h. > > Signed-off-by: Jani Nikula <jani.nikula@intel.com> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> > --- > drivers/gpu/drm/i915/i915_reg.h | 14 +++++++------- > 1 file changed, 7 insertions(+), 7 deletions(-) > > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h > index 2f09145b9791..1eede96a5415 100644 > --- a/drivers/gpu/drm/i915/i915_reg.h > +++ b/drivers/gpu/drm/i915/i915_reg.h > @@ -3292,13 +3292,13 @@ > > #define HSW_STEREO_3D_CTL(dev_priv, trans) _MMIO_PIPE2(dev_priv, trans, _HSW_STEREO_3D_CTL_A) > > -#define _PCH_TRANS_HTOTAL_B 0xe1000 > -#define _PCH_TRANS_HBLANK_B 0xe1004 > -#define _PCH_TRANS_HSYNC_B 0xe1008 > -#define _PCH_TRANS_VTOTAL_B 0xe100c > -#define _PCH_TRANS_VBLANK_B 0xe1010 > -#define _PCH_TRANS_VSYNC_B 0xe1014 > -#define _PCH_TRANS_VSYNCSHIFT_B 0xe1028 > +#define _PCH_TRANS_HTOTAL_B 0xe1000 > +#define _PCH_TRANS_HBLANK_B 0xe1004 > +#define _PCH_TRANS_HSYNC_B 0xe1008 > +#define _PCH_TRANS_VTOTAL_B 0xe100c > +#define _PCH_TRANS_VBLANK_B 0xe1010 > +#define _PCH_TRANS_VSYNC_B 0xe1014 > +#define _PCH_TRANS_VSYNCSHIFT_B 0xe1028 > > #define PCH_TRANS_HTOTAL(pipe) _MMIO_PIPE(pipe, _PCH_TRANS_HTOTAL_A, _PCH_TRANS_HTOTAL_B) > #define PCH_TRANS_HBLANK(pipe) _MMIO_PIPE(pipe, _PCH_TRANS_HBLANK_A, _PCH_TRANS_HBLANK_B) > -- > 2.39.2
On Tue, 10 Sep 2024, Ville Syrjälä <ville.syrjala@linux.intel.com> wrote: > On Tue, Sep 10, 2024 at 04:28:50PM +0300, Jani Nikula wrote: >> Adhere to the style described at the top of i915_reg.h. >> >> Signed-off-by: Jani Nikula <jani.nikula@intel.com> > > Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Thanks, pushed the series to din. Feel free to do your stuff now. BR, Jani. > >> --- >> drivers/gpu/drm/i915/i915_reg.h | 14 +++++++------- >> 1 file changed, 7 insertions(+), 7 deletions(-) >> >> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h >> index 2f09145b9791..1eede96a5415 100644 >> --- a/drivers/gpu/drm/i915/i915_reg.h >> +++ b/drivers/gpu/drm/i915/i915_reg.h >> @@ -3292,13 +3292,13 @@ >> >> #define HSW_STEREO_3D_CTL(dev_priv, trans) _MMIO_PIPE2(dev_priv, trans, _HSW_STEREO_3D_CTL_A) >> >> -#define _PCH_TRANS_HTOTAL_B 0xe1000 >> -#define _PCH_TRANS_HBLANK_B 0xe1004 >> -#define _PCH_TRANS_HSYNC_B 0xe1008 >> -#define _PCH_TRANS_VTOTAL_B 0xe100c >> -#define _PCH_TRANS_VBLANK_B 0xe1010 >> -#define _PCH_TRANS_VSYNC_B 0xe1014 >> -#define _PCH_TRANS_VSYNCSHIFT_B 0xe1028 >> +#define _PCH_TRANS_HTOTAL_B 0xe1000 >> +#define _PCH_TRANS_HBLANK_B 0xe1004 >> +#define _PCH_TRANS_HSYNC_B 0xe1008 >> +#define _PCH_TRANS_VTOTAL_B 0xe100c >> +#define _PCH_TRANS_VBLANK_B 0xe1010 >> +#define _PCH_TRANS_VSYNC_B 0xe1014 >> +#define _PCH_TRANS_VSYNCSHIFT_B 0xe1028 >> >> #define PCH_TRANS_HTOTAL(pipe) _MMIO_PIPE(pipe, _PCH_TRANS_HTOTAL_A, _PCH_TRANS_HTOTAL_B) >> #define PCH_TRANS_HBLANK(pipe) _MMIO_PIPE(pipe, _PCH_TRANS_HBLANK_A, _PCH_TRANS_HBLANK_B) >> -- >> 2.39.2
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 2f09145b9791..1eede96a5415 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -3292,13 +3292,13 @@ #define HSW_STEREO_3D_CTL(dev_priv, trans) _MMIO_PIPE2(dev_priv, trans, _HSW_STEREO_3D_CTL_A) -#define _PCH_TRANS_HTOTAL_B 0xe1000 -#define _PCH_TRANS_HBLANK_B 0xe1004 -#define _PCH_TRANS_HSYNC_B 0xe1008 -#define _PCH_TRANS_VTOTAL_B 0xe100c -#define _PCH_TRANS_VBLANK_B 0xe1010 -#define _PCH_TRANS_VSYNC_B 0xe1014 -#define _PCH_TRANS_VSYNCSHIFT_B 0xe1028 +#define _PCH_TRANS_HTOTAL_B 0xe1000 +#define _PCH_TRANS_HBLANK_B 0xe1004 +#define _PCH_TRANS_HSYNC_B 0xe1008 +#define _PCH_TRANS_VTOTAL_B 0xe100c +#define _PCH_TRANS_VBLANK_B 0xe1010 +#define _PCH_TRANS_VSYNC_B 0xe1014 +#define _PCH_TRANS_VSYNCSHIFT_B 0xe1028 #define PCH_TRANS_HTOTAL(pipe) _MMIO_PIPE(pipe, _PCH_TRANS_HTOTAL_A, _PCH_TRANS_HTOTAL_B) #define PCH_TRANS_HBLANK(pipe) _MMIO_PIPE(pipe, _PCH_TRANS_HBLANK_A, _PCH_TRANS_HBLANK_B)
Adhere to the style described at the top of i915_reg.h. Signed-off-by: Jani Nikula <jani.nikula@intel.com> --- drivers/gpu/drm/i915/i915_reg.h | 14 +++++++------- 1 file changed, 7 insertions(+), 7 deletions(-)