| Message ID | 20181102231320.29164-12-jarkko.sakkinen@linux.intel.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | Intel SGX1 | expand |
On Sat, Nov 3, 2018 at 1:16 AM Jarkko Sakkinen <jarkko.sakkinen@linux.intel.com> wrote: > > SGX defines its own CPUID leaf, 0x12, along with a variable number of > sub-leafs. Sub-leafs 0 and 1 are always available if SGX is supported > and enumerate various SGX features, e.g. instruction sets and enclave > capabilities. Sub-leafs 2+ are variable, both in their existence and > in what they enumerate. Bits 3:0 of EAX report the sub-leaf type, > with the remaining bits in EAX, EBX, ECX and EDX being type-specific. > Currently, the only known sub-leaf type enumerates an EPC section. An > EPC section is simply a range of EPC memory available to software. > The "list" of varaible SGX sub-leafs is NULL-terminated, i.e. software > is expected to query CPUID until an invalid sub-leaf is encountered. > + SGX_CPUID_SUB_LEAF_TYPE_MASK = 0xF, GENMASK() if it suits here? P.S. Btw, BIT() and GENMASK() macros are now in a separate header, i.e. linux/bits.h, perhaps you might need to revisit code to include it explicitly -- With Best Regards, Andy Shevchenko
On Sat, Nov 03, 2018 at 03:11:39PM +0200, Andy Shevchenko wrote: > On Sat, Nov 3, 2018 at 1:16 AM Jarkko Sakkinen > <jarkko.sakkinen@linux.intel.com> wrote: > > > > SGX defines its own CPUID leaf, 0x12, along with a variable number of > > sub-leafs. Sub-leafs 0 and 1 are always available if SGX is supported > > and enumerate various SGX features, e.g. instruction sets and enclave > > capabilities. Sub-leafs 2+ are variable, both in their existence and > > in what they enumerate. Bits 3:0 of EAX report the sub-leaf type, > > with the remaining bits in EAX, EBX, ECX and EDX being type-specific. > > Currently, the only known sub-leaf type enumerates an EPC section. An > > EPC section is simply a range of EPC memory available to software. > > The "list" of varaible SGX sub-leafs is NULL-terminated, i.e. software > > is expected to query CPUID until an invalid sub-leaf is encountered. > > > + SGX_CPUID_SUB_LEAF_TYPE_MASK = 0xF, > > GENMASK() if it suits here? > > P.S. Btw, BIT() and GENMASK() macros are now in a separate header, > i.e. linux/bits.h, perhaps you might need to revisit code to include > it explicitly Agreed. I would also think that is should be renamed simply as SGX_CPUID_SUBLEAF_MASK. /Jarkko
diff --git a/arch/x86/include/asm/sgx_arch.h b/arch/x86/include/asm/sgx_arch.h index d4c57154e6e6..29c37971e8b3 100644 --- a/arch/x86/include/asm/sgx_arch.h +++ b/arch/x86/include/asm/sgx_arch.h @@ -11,6 +11,21 @@ #include <linux/types.h> #include <uapi/asm/sgx_errno.h> +#define SGX_CPUID 0x12 +#define SGX_CPUID_FIRST_VARIABLE_SUB_LEAF 2 + +/** + * enum sgx_sub_leaf_types - SGX CPUID variable sub-leaf types + * %SGX_CPUID_SUB_LEAF_INVALID: Indicates this sub-leaf is invalid. + * %SGX_CPUID_SUB_LEAF_EPC_SECTION: Sub-leaf enumerates an EPC section. + * %SGX_CPUID_SUB_LEAF_TYPE_MASK: Mask for bits containing the type. + */ +enum sgx_sub_leaf_types { + SGX_CPUID_SUB_LEAF_INVALID = 0x0, + SGX_CPUID_SUB_LEAF_EPC_SECTION = 0x1, + SGX_CPUID_SUB_LEAF_TYPE_MASK = 0xF, +}; + /** * enum sgx_encls_leaves - ENCLS leaf functions * %SGX_ECREATE: Create an enclave.