@@ -30,6 +30,7 @@ enum cpuid_leafs
CPUID_7_ECX,
CPUID_8000_0007_EBX,
CPUID_7_EDX,
+ CPUID_12_EAX,
};
#ifdef CONFIG_X86_FEATURE_NAMES
@@ -89,7 +90,7 @@ extern const char * const x86_bug_flags[NBUGINTS*32];
CHECK_BIT_IN_MASK_WORD(REQUIRED_MASK, 17, feature_bit) || \
CHECK_BIT_IN_MASK_WORD(REQUIRED_MASK, 18, feature_bit) || \
REQUIRED_MASK_CHECK || \
- BUILD_BUG_ON_ZERO(NCAPINTS != 19))
+ BUILD_BUG_ON_ZERO(NCAPINTS != 20))
#define DISABLED_MASK_BIT_SET(feature_bit) \
( CHECK_BIT_IN_MASK_WORD(DISABLED_MASK, 0, feature_bit) || \
@@ -112,7 +113,7 @@ extern const char * const x86_bug_flags[NBUGINTS*32];
CHECK_BIT_IN_MASK_WORD(DISABLED_MASK, 17, feature_bit) || \
CHECK_BIT_IN_MASK_WORD(DISABLED_MASK, 18, feature_bit) || \
DISABLED_MASK_CHECK || \
- BUILD_BUG_ON_ZERO(NCAPINTS != 19))
+ BUILD_BUG_ON_ZERO(NCAPINTS != 20))
#define cpu_has(c, bit) \
(__builtin_constant_p(bit) && REQUIRED_MASK_BIT_SET(bit) ? 1 : \
@@ -13,7 +13,7 @@
/*
* Defines x86 CPU feature bits
*/
-#define NCAPINTS 19 /* N 32-bit words worth of info */
+#define NCAPINTS 20 /* N 32-bit words worth of info */
#define NBUGINTS 1 /* N 32-bit bug flags */
/*
@@ -221,22 +221,12 @@
#define X86_FEATURE_L1TF_PTEINV ( 7*32+29) /* "" L1TF workaround PTE inversion */
#define X86_FEATURE_IBRS_ENHANCED ( 7*32+30) /* Enhanced IBRS */
-/*
- * Scattered Intel features: Linux defined, word 8.
- *
- * Note that the bit location of the SGX features is meaningful as KVM expects
- * the Linux defined bit to match the Intel defined bit, e.g. X86_FEATURE_SGX1
- * must remain at bit 0, SGX2 at bit 1, etc...
- */
-#define X86_FEATURE_SGX1 ( 8*32+ 0) /* SGX1 leaf functions */
-#define X86_FEATURE_SGX2 ( 8*32+ 1) /* SGX2 leaf functions */
-/* Bits [0:7] are reserved for SGX */
-
-#define X86_FEATURE_TPR_SHADOW ( 8*32+ 8) /* Intel TPR Shadow */
-#define X86_FEATURE_VNMI ( 8*32+ 9) /* Intel Virtual NMI */
-#define X86_FEATURE_FLEXPRIORITY ( 8*32+10) /* Intel FlexPriority */
-#define X86_FEATURE_EPT ( 8*32+11) /* Intel Extended Page Table */
-#define X86_FEATURE_VPID ( 8*32+12) /* Intel Virtual Processor ID */
+/* Virtualization flags: Linux defined, word 8 */
+#define X86_FEATURE_TPR_SHADOW ( 8*32+ 0) /* Intel TPR Shadow */
+#define X86_FEATURE_VNMI ( 8*32+ 1) /* Intel Virtual NMI */
+#define X86_FEATURE_FLEXPRIORITY ( 8*32+ 2) /* Intel FlexPriority */
+#define X86_FEATURE_EPT ( 8*32+ 3) /* Intel Extended Page Table */
+#define X86_FEATURE_VPID ( 8*32+ 4) /* Intel Virtual Processor ID */
#define X86_FEATURE_VMMCALL ( 8*32+15) /* Prefer VMMCALL to VMCALL */
#define X86_FEATURE_XENPV ( 8*32+16) /* "" Xen paravirtual guest */
@@ -378,6 +368,10 @@
#define X86_FEATURE_ARCH_CAPABILITIES (18*32+29) /* IA32_ARCH_CAPABILITIES MSR (Intel) */
#define X86_FEATURE_SPEC_CTRL_SSBD (18*32+31) /* "" Speculative Store Bypass Disable */
+/* Intel-defined SGX features, CPUID level 0x00000012:0 (EAX), word 19 */
+#define X86_FEATURE_SGX1 (19*32+ 0) /* SGX1 leaf functions */
+#define X86_FEATURE_SGX2 (19*32+ 1) /* SGX2 leaf functions */
+
/*
* BUG word(s)
*/
@@ -44,7 +44,8 @@
# define DISABLE_PCID (1<<(X86_FEATURE_PCID & 31))
# define DISABLE_SGX1 (1<<(X86_FEATURE_SGX1 & 31))
# define DISABLE_SGX2 (1<<(X86_FEATURE_SGX2 & 31))
-#endif /* CONFIG_X86_64 */
+ #endif /* CONFIG_X86_64 */
+
#ifdef CONFIG_X86_INTEL_MEMORY_PROTECTION_KEYS
# define DISABLE_PKU 0
@@ -67,9 +68,9 @@
#endif
#ifdef CONFIG_INTEL_SGX
-# define DISABLE_SGX_CORE 0
+# define DISABLE_SGX_CORE 0
#else
-# define DISABLE_SGX_CORE (1 << (X86_FEATURE_SGX & 31))
+# define DISABLE_SGX_CORE (1 << (X86_FEATURE_SGX & 31))
#endif
/*
@@ -83,7 +84,7 @@
#define DISABLED_MASK5 0
#define DISABLED_MASK6 0
#define DISABLED_MASK7 (DISABLE_PTI)
-#define DISABLED_MASK8 (DISABLE_SGX1|DISABLE_SGX2)
+#define DISABLED_MASK8 0
#define DISABLED_MASK9 (DISABLE_MPX|DISABLE_SMAP|DISABLE_SGX_CORE)
#define DISABLED_MASK10 0
#define DISABLED_MASK11 0
@@ -94,6 +95,7 @@
#define DISABLED_MASK16 (DISABLE_PKU|DISABLE_OSPKE|DISABLE_LA57|DISABLE_UMIP)
#define DISABLED_MASK17 0
#define DISABLED_MASK18 0
-#define DISABLED_MASK_CHECK BUILD_BUG_ON_ZERO(NCAPINTS != 19)
+#define DISABLED_MASK19 (DISABLE_SGX1|DISABLE_SGX2)
+#define DISABLED_MASK_CHECK BUILD_BUG_ON_ZERO(NCAPINTS != 20)
#endif /* _ASM_X86_DISABLED_FEATURES_H */
@@ -101,6 +101,6 @@
#define REQUIRED_MASK16 0
#define REQUIRED_MASK17 0
#define REQUIRED_MASK18 0
-#define REQUIRED_MASK_CHECK BUILD_BUG_ON_ZERO(NCAPINTS != 19)
+#define REQUIRED_MASK_CHECK BUILD_BUG_ON_ZERO(NCAPINTS != 20)
#endif /* _ASM_X86_REQUIRED_FEATURES_H */
@@ -933,6 +933,10 @@ void get_cpu_cap(struct cpuinfo_x86 *c)
c->x86_capability[CPUID_D_1_EAX] = eax;
}
+ /* Additional Intel-defined SGX flags: level 0x00000012 */
+ if (c->cpuid_level >= 0x00000012)
+ c->x86_capability[CPUID_12_EAX] = cpuid_eax(0x00000012);
+
/* AMD-defined flags: level 0x80000001 */
eax = cpuid_eax(0x80000000);
c->extended_cpuid_level = eax;
@@ -35,8 +35,6 @@ static const struct cpuid_bit cpuid_bits[] = {
{ X86_FEATURE_CDP_L3, CPUID_ECX, 2, 0x00000010, 1 },
{ X86_FEATURE_CDP_L2, CPUID_ECX, 2, 0x00000010, 2 },
{ X86_FEATURE_MBA, CPUID_EBX, 3, 0x00000010, 0 },
- { X86_FEATURE_SGX1, CPUID_EAX, 0, 0x00000012, 0 },
- { X86_FEATURE_SGX2, CPUID_EAX, 1, 0x00000012, 0 },
{ X86_FEATURE_HW_PSTATE, CPUID_EDX, 7, 0x80000007, 0 },
{ X86_FEATURE_CPB, CPUID_EDX, 9, 0x80000007, 0 },
{ X86_FEATURE_PROC_FEEDBACK, CPUID_EDX, 11, 0x80000007, 0 },
@@ -13,7 +13,7 @@
/*
* Defines x86 CPU feature bits
*/
-#define NCAPINTS 19 /* N 32-bit words worth of info */
+#define NCAPINTS 20 /* N 32-bit words worth of info */
#define NBUGINTS 1 /* N 32-bit bug flags */
/*
@@ -221,21 +221,12 @@
#define X86_FEATURE_L1TF_PTEINV ( 7*32+29) /* "" L1TF workaround PTE inversion */
#define X86_FEATURE_IBRS_ENHANCED ( 7*32+30) /* Enhanced IBRS */
-/*
- * Scattered Intel features: Linux defined, word 8.
- *
- * Note that the bit numbers of the SGX features are meaningful as KVM expects
- * the Linux defined bit to match the Intel defined bit, e.g. X86_FEATURE_SGX1
- * must remain at bit 0, SGX2 at bit 1, etc...
- */
-#define X86_FEATURE_SGX1 ( 8*32+ 0) /* SGX1 leaf functions */
-#define X86_FEATURE_SGX2 ( 8*32+ 1) /* SGX2 leaf functions */
-
-#define X86_FEATURE_TPR_SHADOW ( 8*32+ 8) /* Intel TPR Shadow */
-#define X86_FEATURE_VNMI ( 8*32+ 9) /* Intel Virtual NMI */
-#define X86_FEATURE_FLEXPRIORITY ( 8*32+10) /* Intel FlexPriority */
-#define X86_FEATURE_EPT ( 8*32+11) /* Intel Extended Page Table */
-#define X86_FEATURE_VPID ( 8*32+12) /* Intel Virtual Processor ID */
+/* Virtualization flags: Linux defined, word 8 */
+#define X86_FEATURE_TPR_SHADOW ( 8*32+ 0) /* Intel TPR Shadow */
+#define X86_FEATURE_VNMI ( 8*32+ 1) /* Intel Virtual NMI */
+#define X86_FEATURE_FLEXPRIORITY ( 8*32+ 2) /* Intel FlexPriority */
+#define X86_FEATURE_EPT ( 8*32+ 3) /* Intel Extended Page Table */
+#define X86_FEATURE_VPID ( 8*32+ 4) /* Intel Virtual Processor ID */
#define X86_FEATURE_VMMCALL ( 8*32+15) /* Prefer VMMCALL to VMCALL */
#define X86_FEATURE_XENPV ( 8*32+16) /* "" Xen paravirtual guest */
@@ -246,6 +237,7 @@
/* Intel-defined CPU features, CPUID level 0x00000007:0 (EBX), word 9 */
#define X86_FEATURE_FSGSBASE ( 9*32+ 0) /* RDFSBASE, WRFSBASE, RDGSBASE, WRGSBASE instructions*/
#define X86_FEATURE_TSC_ADJUST ( 9*32+ 1) /* TSC adjustment MSR 0x3B */
+#define X86_FEATURE_SGX ( 9*32+ 2) /* Software Guard Extensions */
#define X86_FEATURE_BMI1 ( 9*32+ 3) /* 1st group bit manipulation extensions */
#define X86_FEATURE_HLE ( 9*32+ 4) /* Hardware Lock Elision */
#define X86_FEATURE_AVX2 ( 9*32+ 5) /* AVX2 instructions */
@@ -375,6 +367,10 @@
#define X86_FEATURE_ARCH_CAPABILITIES (18*32+29) /* IA32_ARCH_CAPABILITIES MSR (Intel) */
#define X86_FEATURE_SPEC_CTRL_SSBD (18*32+31) /* "" Speculative Store Bypass Disable */
+/* Intel-defined SGX features, CPUID level 0x00000012:0 (EAX), word 19 */
+#define X86_FEATURE_SGX1 (19*32+ 0) /* SGX1 leaf functions */
+#define X86_FEATURE_SGX2 (19*32+ 1) /* SGX2 leaf functions */
+
/*
* BUG word(s)
*/
As requested by Boris, move the CPUID 0x12 features to their own word in cpufeatures. This can be squashed cleanly with commit c3eac55d3882 ("x86/cpufeatures: x86/msr: Add Intel SGX hardware bits"), replacing paragraph Remap CPUID.(EAX=12H, ECX=0) bits to the Linux fake CPUID 8 in order to conserve some space. Keep the bit positions intact because KVM requires this. Reserve bits 0-7 for SGX in order to maintain this invariant also when new SGX specific feature bits get added. with Add the SGX sub-features in a new word even though only two bits will be used in the immediate future. KVM support for SGX is expected in the not-too-distant future, and having a dedicated feature word allows KVM to include SGX sub-features in its reserve-cpuid lookup table, e.g. to easily query guest CPUID capabilities. Signed-off-by: Sean Christopherson <sean.j.christopherson@intel.com> --- arch/x86/include/asm/cpufeature.h | 5 +++-- arch/x86/include/asm/cpufeatures.h | 28 ++++++++++-------------- arch/x86/include/asm/disabled-features.h | 12 +++++----- arch/x86/include/asm/required-features.h | 2 +- arch/x86/kernel/cpu/common.c | 4 ++++ arch/x86/kernel/cpu/scattered.c | 2 -- tools/arch/x86/include/asm/cpufeatures.h | 28 ++++++++++-------------- 7 files changed, 38 insertions(+), 43 deletions(-)