From patchwork Mon May 18 16:07:19 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Pierre Morel X-Patchwork-Id: 11555653 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id CE434739 for ; Mon, 18 May 2020 16:07:39 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id BD068207D8 for ; Mon, 18 May 2020 16:07:39 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728271AbgERQHj (ORCPT ); Mon, 18 May 2020 12:07:39 -0400 Received: from mx0a-001b2d01.pphosted.com ([148.163.156.1]:55078 "EHLO mx0a-001b2d01.pphosted.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727005AbgERQHj (ORCPT ); Mon, 18 May 2020 12:07:39 -0400 Received: from pps.filterd (m0098399.ppops.net [127.0.0.1]) by mx0a-001b2d01.pphosted.com (8.16.0.42/8.16.0.42) with SMTP id 04IG1naA046194; Mon, 18 May 2020 12:07:38 -0400 Received: from pps.reinject (localhost [127.0.0.1]) by mx0a-001b2d01.pphosted.com with ESMTP id 312cayexp0-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Mon, 18 May 2020 12:07:37 -0400 Received: from m0098399.ppops.net (m0098399.ppops.net [127.0.0.1]) by pps.reinject (8.16.0.36/8.16.0.36) with SMTP id 04IG1ol1046319; Mon, 18 May 2020 12:07:37 -0400 Received: from ppma04ams.nl.ibm.com (63.31.33a9.ip4.static.sl-reverse.com [169.51.49.99]) by mx0a-001b2d01.pphosted.com with ESMTP id 312cayexn3-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Mon, 18 May 2020 12:07:37 -0400 Received: from pps.filterd (ppma04ams.nl.ibm.com [127.0.0.1]) by ppma04ams.nl.ibm.com (8.16.0.27/8.16.0.27) with SMTP id 04IG5dBY016149; Mon, 18 May 2020 16:07:35 GMT Received: from b06avi18878370.portsmouth.uk.ibm.com (b06avi18878370.portsmouth.uk.ibm.com [9.149.26.194]) by ppma04ams.nl.ibm.com with ESMTP id 3127t5mf8y-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Mon, 18 May 2020 16:07:35 +0000 Received: from d06av25.portsmouth.uk.ibm.com (d06av25.portsmouth.uk.ibm.com [9.149.105.61]) by b06avi18878370.portsmouth.uk.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id 04IG7XEX61866272 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Mon, 18 May 2020 16:07:33 GMT Received: from d06av25.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id D98E811C050; Mon, 18 May 2020 16:07:32 +0000 (GMT) Received: from d06av25.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 8326911C04A; Mon, 18 May 2020 16:07:32 +0000 (GMT) Received: from oc3016276355.ibm.com (unknown [9.145.158.244]) by d06av25.portsmouth.uk.ibm.com (Postfix) with ESMTP; Mon, 18 May 2020 16:07:32 +0000 (GMT) From: Pierre Morel To: kvm@vger.kernel.org Cc: linux-s390@vger.kernel.org, frankja@linux.ibm.com, david@redhat.com, thuth@redhat.com, cohuck@redhat.com Subject: [kvm-unit-tests PATCH v7 00/12] s390x: Testing the Channel Subsystem I/O Date: Mon, 18 May 2020 18:07:19 +0200 Message-Id: <1589818051-20549-1-git-send-email-pmorel@linux.ibm.com> X-Mailer: git-send-email 1.8.3.1 X-TM-AS-GCONF: 00 X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.216,18.0.676 definitions=2020-05-18_06:2020-05-15,2020-05-18 signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 phishscore=0 lowpriorityscore=0 mlxscore=0 suspectscore=1 spamscore=0 impostorscore=0 malwarescore=0 adultscore=0 bulkscore=0 clxscore=1015 mlxlogscore=999 priorityscore=1501 cotscore=-2147483648 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2004280000 definitions=main-2005180134 Sender: kvm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org Goal of the series is to have a framework to test Channel-Subsystem I/O with QEMU/KVM. To be able to support interrupt for CSS I/O and for SCLP we need to modify the interrupt framework to allow re-entrant interruptions. We add a registration for IRQ callbacks to the test program to define its own interrupt handler. We need to do special work under interrupt like acknowledging the interrupt. Being working on PSW bits to allow I/O interrupt, we define new PSW bits in arch_def.h and use __ASSEMBLER__ define to be able to include this header in an assembler source file. This series presents four major tests: - Enumeration: The CSS is enumerated using the STSCH instruction recursively on all potentially existing channels. Keeping the first channel found as a reference for future use. Checks STSCH - Enable: If the enumeration succeeded the tests enables the reference channel with MSCH and verifies with STSCH that the channel is effectively enabled, retrying a predefined count on failure to enable the channel Checks MSCH - Sense: If the channel is enabled this test sends a SENSE_ID command to the reference channel, analyzing the answer and expecting the Control unit type being 0xc0ca Checks SSCH(READ) and IO-IRQ - ping-pong: If the reference channel leads to the PONG device (0xc0ca), the test exchanges a string containing a 9 digit number with the PONG device and expecting this number to be incremented by the PONG device. Checks SSCH(WRITE) Note: - The following patches may be pulled first: s390x: saving regs for interrupts s390x: Use PSW bits definitions in cstart s390x: Move control register bit definitions and add AFP to them s390x: export the clock get_clock_ms() utility s390x: use get_clock_ms() to calculate a delay in ms - I think this one if it receives reviewed-by can also be pulled now: s390x: define function to wait for interrupt - this patch has a comment from Janosch who asks change so... need opinion: but since I need reviews for the next patches I let it here unchanged. s390x: interrupt registration - These 5 patches are really I/O oriented and need reviewed-by: s390x: Library resources for CSS tests s390x: css: stsch, enumeration test s390x: css: msch, enable test s390x: css: ssch/tsch with sense and interrupt s390x: css: ping pong Regards, Pierre Pierre Morel (12): s390x: saving regs for interrupts s390x: Use PSW bits definitions in cstart s390x: Move control register bit definitions and add AFP to them s390x: interrupt registration s390x: export the clock get_clock_ms() utility s390x: use get_clock_ms() to calculate a delay in ms s390x: Library resources for CSS tests s390x: css: stsch, enumeration test s390x: css: msch, enable test s390x: define function to wait for interrupt s390x: css: ssch/tsch with sense and interrupt s390x: css: ping pong lib/s390x/asm/arch_def.h | 32 +++- lib/s390x/asm/time.h | 36 ++++ lib/s390x/css.h | 279 ++++++++++++++++++++++++++++++ lib/s390x/css_dump.c | 157 +++++++++++++++++ lib/s390x/css_lib.c | 55 ++++++ lib/s390x/interrupt.c | 23 ++- lib/s390x/interrupt.h | 8 + s390x/Makefile | 3 + s390x/css.c | 355 +++++++++++++++++++++++++++++++++++++++ s390x/cstart64.S | 58 +++++-- s390x/intercept.c | 11 +- s390x/unittests.cfg | 4 + 12 files changed, 995 insertions(+), 26 deletions(-) create mode 100644 lib/s390x/asm/time.h create mode 100644 lib/s390x/css.h create mode 100644 lib/s390x/css_dump.c create mode 100644 lib/s390x/css_lib.c create mode 100644 lib/s390x/interrupt.h create mode 100644 s390x/css.c