| Message ID | 1594088183-7187-1-git-send-email-cathy.zhang@intel.com (mailing list archive) |
|---|---|
| Headers | show |
| Series | Expose new features for intel processor | expand |
>Cathy Zhang (2): > x86: Expose SERIALIZE for supported cpuid > x86: Expose TSX Suspend Load Address Tracking Having separate patches for adding the X86_FEATURE bits is fine (provides space in the commit log to document what each is for). In this case it also preserves the "Author" of each. But you should combine patches 3 & 4 into a single patch. Making two patches to each add one bit to the KVM cpuid code just looks like you are trying to inflate your patch count. -Tony
This patchset is to expose two new features for intel processors which support them, like Sapphire Rapids. SERIALIZE is a faster serializing instruction which does not modify registers, arithmetic flags or memory, will not cause VM exit. TSX suspend load tracking instruction aims to give a way to choose which memory accesses do not need to be tracked in the TSX read set. Changelog: v2 Add kernel feature enumeration patch to fix build error Cathy Zhang (2): x86: Expose SERIALIZE for supported cpuid x86: Expose TSX Suspend Load Address Tracking Ricardo Neri (1): x86/cpufeatures: Add enumeration for SERIALIZE instruction Kyung Min Park (1): x86/cpufeatures: Enumerate TSX suspend load address tracking instructions arch/x86/include/asm/cpufeatures.h | 2 ++ arch/x86/kvm/cpuid.c | 3 ++- 2 files changed, 4 insertions(+), 1 deletion(-) -- 1.8.3.1