| Message ID | 1607545670-1557-1-git-send-email-mjrosato@linux.ibm.com (mailing list archive) |
|---|---|
| Headers | show |
| Series | vfio-pci/zdev: Fixing s390 vfio-pci ISM support | expand |
On 12/9/20 3:27 PM, Matthew Rosato wrote: > Today, ISM devices are completely disallowed for vfio-pci passthrough as > QEMU will reject the device due to an (inappropriate) MSI-X check. > However, in an effort to enable ISM device passthrough, I realized that the > manner in which ISM performs block write operations is highly incompatible > with the way that QEMU s390 PCI instruction interception and > vfio_pci_bar_rw break up I/O operations into 8B and 4B operations -- ISM > devices have particular requirements in regards to the alignment, size and > order of writes performed. Furthermore, they require that legacy/non-MIO > s390 PCI instructions are used, which is also not guaranteed when the I/O > is passed through the typical userspace channels. > > As a result, this patchset proposes a new VFIO region to allow a guest to > pass certain PCI instruction intercepts directly to the s390 host kernel > PCI layer for exeuction, pinning the guest buffer in memory briefly in > order to execute the requested PCI instruction. > > Matthew Rosato (4): > s390/pci: track alignment/length strictness for zpci_dev > vfio-pci/zdev: Pass the relaxed alignment flag > s390/pci: Get hardware-reported max store block length > vfio-pci/zdev: Introduce the zPCI I/O vfio region > > arch/s390/include/asm/pci.h | 4 +- > arch/s390/include/asm/pci_clp.h | 7 +- > arch/s390/pci/pci_clp.c | 2 + > drivers/vfio/pci/vfio_pci.c | 8 ++ > drivers/vfio/pci/vfio_pci_private.h | 6 ++ > drivers/vfio/pci/vfio_pci_zdev.c | 160 ++++++++++++++++++++++++++++++++++++ > include/uapi/linux/vfio.h | 4 + > include/uapi/linux/vfio_zdev.h | 33 ++++++++ > 8 files changed, 221 insertions(+), 3 deletions(-) > Associated qemu patchset: https://lists.gnu.org/archive/html/qemu-devel/2020-12/msg02377.html
On Wed, 9 Dec 2020 15:27:46 -0500 Matthew Rosato <mjrosato@linux.ibm.com> wrote: > Today, ISM devices are completely disallowed for vfio-pci passthrough as > QEMU will reject the device due to an (inappropriate) MSI-X check. > However, in an effort to enable ISM device passthrough, I realized that the > manner in which ISM performs block write operations is highly incompatible > with the way that QEMU s390 PCI instruction interception and > vfio_pci_bar_rw break up I/O operations into 8B and 4B operations -- ISM > devices have particular requirements in regards to the alignment, size and > order of writes performed. Furthermore, they require that legacy/non-MIO > s390 PCI instructions are used, which is also not guaranteed when the I/O > is passed through the typical userspace channels. The part about the non-MIO instructions confuses me. How can MIO instructions be generated with the current code, and why does changing the write pattern help? > > As a result, this patchset proposes a new VFIO region to allow a guest to > pass certain PCI instruction intercepts directly to the s390 host kernel > PCI layer for exeuction, pinning the guest buffer in memory briefly in > order to execute the requested PCI instruction. > > Matthew Rosato (4): > s390/pci: track alignment/length strictness for zpci_dev > vfio-pci/zdev: Pass the relaxed alignment flag > s390/pci: Get hardware-reported max store block length > vfio-pci/zdev: Introduce the zPCI I/O vfio region > > arch/s390/include/asm/pci.h | 4 +- > arch/s390/include/asm/pci_clp.h | 7 +- > arch/s390/pci/pci_clp.c | 2 + > drivers/vfio/pci/vfio_pci.c | 8 ++ > drivers/vfio/pci/vfio_pci_private.h | 6 ++ > drivers/vfio/pci/vfio_pci_zdev.c | 160 ++++++++++++++++++++++++++++++++++++ > include/uapi/linux/vfio.h | 4 + > include/uapi/linux/vfio_zdev.h | 33 ++++++++ > 8 files changed, 221 insertions(+), 3 deletions(-) >
On 12/10/20 7:33 AM, Cornelia Huck wrote: > On Wed, 9 Dec 2020 15:27:46 -0500 > Matthew Rosato <mjrosato@linux.ibm.com> wrote: > >> Today, ISM devices are completely disallowed for vfio-pci passthrough as >> QEMU will reject the device due to an (inappropriate) MSI-X check. >> However, in an effort to enable ISM device passthrough, I realized that the >> manner in which ISM performs block write operations is highly incompatible >> with the way that QEMU s390 PCI instruction interception and >> vfio_pci_bar_rw break up I/O operations into 8B and 4B operations -- ISM >> devices have particular requirements in regards to the alignment, size and >> order of writes performed. Furthermore, they require that legacy/non-MIO >> s390 PCI instructions are used, which is also not guaranteed when the I/O >> is passed through the typical userspace channels. > > The part about the non-MIO instructions confuses me. How can MIO > instructions be generated with the current code, and why does changing So to be clear, they are not being generated at all in the guest as the necessary facility is reported as unavailable. Let's talk about Linux in LPAR / the host kernel: When hardware that supports MIO instructions is available, all userspace I/O traffic is going to be routed through the MIO variants of the s390 PCI instructions. This is working well for other device types, but does not work for ISM which does not support these variants. However, the ISM driver also does not invoke the userspace I/O routines for the kernel, it invokes the s390 PCI layer directly, which in turn ensures the proper PCI instructions are used -- This approach falls apart when the guest ISM driver invokes those routines in the guest -- we (qemu) pass those non-MIO instructions from the guest as memory operations through vfio-pci, traversing through the vfio I/O layer in the guest (vfio_pci_bar_rw and friends), where we then arrive in the host s390 PCI layer -- where the MIO variant is used because the facility is available. Per conversations with Niklas (on CC), it's not trivial to decide by the time we reach the s390 PCI I/O layer to switch gears and use the non-MIO instruction set. > the write pattern help? The write pattern is a separate issue from non-MIO instruction requirements... Certain address spaces require specific instructions to be used (so, no substituting PCISTG for PCISTB - that happens too by default for any writes coming into the host s390 PCI layer that are <=8B, and they all are when the PCISTB is broken up into 8B memory operations that travel through vfio_pci_bar_rw, which further breaks those up into 4B operations). There's also a requirement for some writes that the data, if broken up, be written in a certain order in order to properly trigger events. :( The ability to pass the entire PCISTB payload vs breaking it into 8B chunks is also significantly faster. > >> >> As a result, this patchset proposes a new VFIO region to allow a guest to >> pass certain PCI instruction intercepts directly to the s390 host kernel >> PCI layer for exeuction, pinning the guest buffer in memory briefly in >> order to execute the requested PCI instruction. >> >> Matthew Rosato (4): >> s390/pci: track alignment/length strictness for zpci_dev >> vfio-pci/zdev: Pass the relaxed alignment flag >> s390/pci: Get hardware-reported max store block length >> vfio-pci/zdev: Introduce the zPCI I/O vfio region >> >> arch/s390/include/asm/pci.h | 4 +- >> arch/s390/include/asm/pci_clp.h | 7 +- >> arch/s390/pci/pci_clp.c | 2 + >> drivers/vfio/pci/vfio_pci.c | 8 ++ >> drivers/vfio/pci/vfio_pci_private.h | 6 ++ >> drivers/vfio/pci/vfio_pci_zdev.c | 160 ++++++++++++++++++++++++++++++++++++ >> include/uapi/linux/vfio.h | 4 + >> include/uapi/linux/vfio_zdev.h | 33 ++++++++ >> 8 files changed, 221 insertions(+), 3 deletions(-) >> >
On 12/10/20 4:51 PM, Matthew Rosato wrote: > On 12/10/20 7:33 AM, Cornelia Huck wrote: >> On Wed, 9 Dec 2020 15:27:46 -0500 >> Matthew Rosato <mjrosato@linux.ibm.com> wrote: >> >>> Today, ISM devices are completely disallowed for vfio-pci passthrough as >>> QEMU will reject the device due to an (inappropriate) MSI-X check. >>> However, in an effort to enable ISM device passthrough, I realized that the >>> manner in which ISM performs block write operations is highly incompatible >>> with the way that QEMU s390 PCI instruction interception and >>> vfio_pci_bar_rw break up I/O operations into 8B and 4B operations -- ISM >>> devices have particular requirements in regards to the alignment, size and >>> order of writes performed. Furthermore, they require that legacy/non-MIO >>> s390 PCI instructions are used, which is also not guaranteed when the I/O >>> is passed through the typical userspace channels. >> >> The part about the non-MIO instructions confuses me. How can MIO >> instructions be generated with the current code, and why does changing > > So to be clear, they are not being generated at all in the guest as the necessary facility is reported as unavailable. > > Let's talk about Linux in LPAR / the host kernel: When hardware that supports MIO instructions is available, all userspace I/O traffic is going to be routed through the MIO variants of the s390 PCI instructions. This is working well for other device types, but does not work for ISM which does not support these variants. However, the ISM driver also does not invoke the userspace I/O routines for the kernel, it invokes the s390 PCI layer directly, which in turn ensures the proper PCI instructions are used -- This approach falls apart when the guest ISM driver invokes those routines in the guest -- we (qemu) pass those non-MIO instructions from the guest as memory operations through vfio-pci, traversing through the vfio I/O layer in the guest (vfio_pci_bar_rw and friends), where we then arrive in the host s390 PCI layer -- where the MIO variant is used because the facility is available. Slight clarification since I think the word "userspace" is a bit overloaded as KVM folks often use it to talk about the guest even when that calls through vfio. Application userspace (i.e. things like DPDK) can use PCI MIO Load/Stores directly on mmap()ed/ioremap()ed memory these don't go through the Kernel at all. QEMU while also in userspace on the other hand goes through the vfio_bar_rw() region which uses the common code _Kernel_ ioread()/iowrite() API. This Kernel ioread()/iowrite() API uses PCI MIO Load/Stores by default on machines that support them (z15 currently). The ISM driver, knowing that its device does not support MIO, goes around this API and directly calls zpci_store()/zpci_load(). > > Per conversations with Niklas (on CC), it's not trivial to decide by the time we reach the s390 PCI I/O layer to switch gears and use the non-MIO instruction set. Yes, we have some ideas about dynamically switching to legacy PCI stores in ioread()/iowrite() for devices that are set up for it but since that only gets an ioremap()ed address, a value and a size it would evolve such nasty things as looking at this virtual address to determine if it includes a ZPCI_ADDR() cookie that we use to get to the function handle needed for the legacy PCI Load/Stores, while MIO PCI Load/Stores directly work on virtual addresses. Now purely for the Kernel API we think this could work since that always allocates between VMALLOC_START and VMALLOC_END and we control where we put the ZPCI_ADDR() cookie but I'm very hesitant to add something like that. As for application userspace (DPDK) we do have a syscall (arch/s390/pci/pci_mmio.c) API that had a similar problem but we could make use of the fact that our Architecture is pretty nifty with address spaces and just execute the MIO PCI Load/Store in the syscall _as if_ by the calling userspace application. > >> the write pattern help? > ... snip ...
On Thu, 10 Dec 2020 17:14:24 +0100 Niklas Schnelle <schnelle@linux.ibm.com> wrote: > On 12/10/20 4:51 PM, Matthew Rosato wrote: > > On 12/10/20 7:33 AM, Cornelia Huck wrote: > >> On Wed, 9 Dec 2020 15:27:46 -0500 > >> Matthew Rosato <mjrosato@linux.ibm.com> wrote: > >> > >>> Today, ISM devices are completely disallowed for vfio-pci passthrough as > >>> QEMU will reject the device due to an (inappropriate) MSI-X check. > >>> However, in an effort to enable ISM device passthrough, I realized that the > >>> manner in which ISM performs block write operations is highly incompatible > >>> with the way that QEMU s390 PCI instruction interception and > >>> vfio_pci_bar_rw break up I/O operations into 8B and 4B operations -- ISM > >>> devices have particular requirements in regards to the alignment, size and > >>> order of writes performed. Furthermore, they require that legacy/non-MIO > >>> s390 PCI instructions are used, which is also not guaranteed when the I/O > >>> is passed through the typical userspace channels. > >> > >> The part about the non-MIO instructions confuses me. How can MIO > >> instructions be generated with the current code, and why does changing > > > > So to be clear, they are not being generated at all in the guest as the necessary facility is reported as unavailable. > > > > Let's talk about Linux in LPAR / the host kernel: When hardware that supports MIO instructions is available, all userspace I/O traffic is going to be routed through the MIO variants of the s390 PCI instructions. This is working well for other device types, but does not work for ISM which does not support these variants. However, the ISM driver also does not invoke the userspace I/O routines for the kernel, it invokes the s390 PCI layer directly, which in turn ensures the proper PCI instructions are used -- This approach falls apart when the guest ISM driver invokes those routines in the guest -- we (qemu) pass those non-MIO instructions from the guest as memory operations through vfio-pci, traversing through the vfio I/O layer in the guest (vfio_pci_bar_rw and friends), where we then arrive in the host s390 PCI layer -- where the MIO variant is used because the facility is available. > > Slight clarification since I think the word "userspace" is a bit overloaded as > KVM folks often use it to talk about the guest even when that calls through vfio. > Application userspace (i.e. things like DPDK) can use PCI MIO Load/Stores > directly on mmap()ed/ioremap()ed memory these don't go through the Kernel at > all. > QEMU while also in userspace on the other hand goes through the vfio_bar_rw() > region which uses the common code _Kernel_ ioread()/iowrite() API. This Kernel > ioread()/iowrite() API uses PCI MIO Load/Stores by default on machines that > support them (z15 currently). The ISM driver, knowing that its device does not > support MIO, goes around this API and directly calls zpci_store()/zpci_load(). Ok, thanks for the explanation. > > > > > > Per conversations with Niklas (on CC), it's not trivial to decide by the time we reach the s390 PCI I/O layer to switch gears and use the non-MIO instruction set. > > Yes, we have some ideas about dynamically switching to legacy PCI stores in > ioread()/iowrite() for devices that are set up for it but since that only gets > an ioremap()ed address, a value and a size it would evolve such nasty things as > looking at this virtual address to determine if it includes a ZPCI_ADDR() > cookie that we use to get to the function handle needed for the legacy PCI > Load/Stores, while MIO PCI Load/Stores directly work on virtual addresses. > > Now purely for the Kernel API we think this could work since that always > allocates between VMALLOC_START and VMALLOC_END and we control where we put the > ZPCI_ADDR() cookie but I'm very hesitant to add something like that. > > As for application userspace (DPDK) we do have a syscall > (arch/s390/pci/pci_mmio.c) API that had a similar problem but we could make use > of the fact that our Architecture is pretty nifty with address spaces and just > execute the MIO PCI Load/Store in the syscall _as if_ by the calling userspace > application. Is ISM (currently) the only device that needs to use the non-MIO instructions, or are there others as well? Is there any characteristic that a meta driver like vfio could discover, or is it a device quirk you just need to know about?
On Thu, 10 Dec 2020 10:51:23 -0500 Matthew Rosato <mjrosato@linux.ibm.com> wrote: > On 12/10/20 7:33 AM, Cornelia Huck wrote: > > On Wed, 9 Dec 2020 15:27:46 -0500 > > Matthew Rosato <mjrosato@linux.ibm.com> wrote: > > > >> Today, ISM devices are completely disallowed for vfio-pci passthrough as > >> QEMU will reject the device due to an (inappropriate) MSI-X check. > >> However, in an effort to enable ISM device passthrough, I realized that the > >> manner in which ISM performs block write operations is highly incompatible > >> with the way that QEMU s390 PCI instruction interception and > >> vfio_pci_bar_rw break up I/O operations into 8B and 4B operations -- ISM > >> devices have particular requirements in regards to the alignment, size and > >> order of writes performed. Furthermore, they require that legacy/non-MIO > >> s390 PCI instructions are used, which is also not guaranteed when the I/O > >> is passed through the typical userspace channels. > > > > The part about the non-MIO instructions confuses me. How can MIO > > instructions be generated with the current code, and why does changing > > So to be clear, they are not being generated at all in the guest as the > necessary facility is reported as unavailable. > > Let's talk about Linux in LPAR / the host kernel: When hardware that > supports MIO instructions is available, all userspace I/O traffic is > going to be routed through the MIO variants of the s390 PCI > instructions. This is working well for other device types, but does not > work for ISM which does not support these variants. However, the ISM > driver also does not invoke the userspace I/O routines for the kernel, > it invokes the s390 PCI layer directly, which in turn ensures the proper > PCI instructions are used -- This approach falls apart when the guest > ISM driver invokes those routines in the guest -- we (qemu) pass those > non-MIO instructions from the guest as memory operations through > vfio-pci, traversing through the vfio I/O layer in the guest > (vfio_pci_bar_rw and friends), where we then arrive in the host s390 PCI > layer -- where the MIO variant is used because the facility is available. > > Per conversations with Niklas (on CC), it's not trivial to decide by the > time we reach the s390 PCI I/O layer to switch gears and use the non-MIO > instruction set. > > > the write pattern help? > > The write pattern is a separate issue from non-MIO instruction > requirements... Certain address spaces require specific instructions to > be used (so, no substituting PCISTG for PCISTB - that happens too by > default for any writes coming into the host s390 PCI layer that are > <=8B, and they all are when the PCISTB is broken up into 8B memory > operations that travel through vfio_pci_bar_rw, which further breaks > those up into 4B operations). There's also a requirement for some > writes that the data, if broken up, be written in a certain order in > order to properly trigger events. :( The ability to pass the entire > PCISTB payload vs breaking it into 8B chunks is also significantly faster. Let me summarize this to make sure I understand this new region correctly: - some devices may have relaxed alignment/length requirements for pcistb (and friends?) - some devices may actually require writes to be done in a large chunk instead of being broken up (is that a strict subset of the devices above?) - some devices do not support the new MIO instructions (is that a subset of the relaxed alignment devices? I'm not familiar with the MIO instructions) The patchsets introduce a new region that (a) is used by QEMU to submit writes in one go, and (b) makes sure to call into the non-MIO instructions directly; it's basically killing two birds with one stone for ISM devices. Are these two requirements (large writes and non-MIO) always going hand-in-hand, or is ISM just an odd device? If there's an expectation that the new region will always use the non-MIO instructions (in addition to the changed write handling), it should be noted in the description for the region as well.
On 12/11/20 9:35 AM, Cornelia Huck wrote: > On Thu, 10 Dec 2020 10:51:23 -0500 > Matthew Rosato <mjrosato@linux.ibm.com> wrote: > >> On 12/10/20 7:33 AM, Cornelia Huck wrote: >>> On Wed, 9 Dec 2020 15:27:46 -0500 >>> Matthew Rosato <mjrosato@linux.ibm.com> wrote: >>> >>>> Today, ISM devices are completely disallowed for vfio-pci passthrough as >>>> QEMU will reject the device due to an (inappropriate) MSI-X check. >>>> However, in an effort to enable ISM device passthrough, I realized that the >>>> manner in which ISM performs block write operations is highly incompatible >>>> with the way that QEMU s390 PCI instruction interception and >>>> vfio_pci_bar_rw break up I/O operations into 8B and 4B operations -- ISM >>>> devices have particular requirements in regards to the alignment, size and >>>> order of writes performed. Furthermore, they require that legacy/non-MIO >>>> s390 PCI instructions are used, which is also not guaranteed when the I/O >>>> is passed through the typical userspace channels. >>> >>> The part about the non-MIO instructions confuses me. How can MIO >>> instructions be generated with the current code, and why does changing >> >> So to be clear, they are not being generated at all in the guest as the >> necessary facility is reported as unavailable. >> >> Let's talk about Linux in LPAR / the host kernel: When hardware that >> supports MIO instructions is available, all userspace I/O traffic is >> going to be routed through the MIO variants of the s390 PCI >> instructions. This is working well for other device types, but does not >> work for ISM which does not support these variants. However, the ISM >> driver also does not invoke the userspace I/O routines for the kernel, >> it invokes the s390 PCI layer directly, which in turn ensures the proper >> PCI instructions are used -- This approach falls apart when the guest >> ISM driver invokes those routines in the guest -- we (qemu) pass those >> non-MIO instructions from the guest as memory operations through >> vfio-pci, traversing through the vfio I/O layer in the guest >> (vfio_pci_bar_rw and friends), where we then arrive in the host s390 PCI >> layer -- where the MIO variant is used because the facility is available. >> >> Per conversations with Niklas (on CC), it's not trivial to decide by the >> time we reach the s390 PCI I/O layer to switch gears and use the non-MIO >> instruction set. >> >>> the write pattern help? >> >> The write pattern is a separate issue from non-MIO instruction >> requirements... Certain address spaces require specific instructions to >> be used (so, no substituting PCISTG for PCISTB - that happens too by >> default for any writes coming into the host s390 PCI layer that are >> <=8B, and they all are when the PCISTB is broken up into 8B memory >> operations that travel through vfio_pci_bar_rw, which further breaks >> those up into 4B operations). There's also a requirement for some >> writes that the data, if broken up, be written in a certain order in >> order to properly trigger events. :( The ability to pass the entire >> PCISTB payload vs breaking it into 8B chunks is also significantly faster. > > Let me summarize this to make sure I understand this new region > correctly: > > - some devices may have relaxed alignment/length requirements for > pcistb (and friends?) The relaxed alignment bit is really specific to PCISTB behavior, so the "and friends" doesn't apply there. > - some devices may actually require writes to be done in a large chunk > instead of being broken up (is that a strict subset of the devices > above?) Yes, this is specific to ISM devices, which are always a relaxed alignment/length device. The inverse is an interesting question though (relaxed alignment devices that are not ISM, which you've posed as a possible future extension for emulated devices). I'm not sure that any (real devices) exist where (relaxed_alignment && !ism), but 'what if' -- I guess the right approach would mean additional code in QEMU to handle relaxed alignment for the vfio mmio path as well (seen as pcistb_default in my qemu patchset) and being very specific in QEMU to only enable the region for an ism device. > - some devices do not support the new MIO instructions (is that a > subset of the relaxed alignment devices? I'm not familiar with the > MIO instructions) > The non-MIO requirement is again specific to ISM, which is a subset of the relaxed alignment devices. In this case, the requirement is not limited to PCISTB, and that's why PCILG is also included here. The ISM driver does not use PCISTG, and the only PCISTG instructions coming from the guest against an ISM device would be against the config space and those are OK to go through vfio still; so what was provided via the region is effectively the bare-minimum requirement to allow ISM to function properly in the guest. > The patchsets introduce a new region that (a) is used by QEMU to submit > writes in one go, and (b) makes sure to call into the non-MIO > instructions directly; it's basically killing two birds with one stone > for ISM devices. Are these two requirements (large writes and non-MIO) > always going hand-in-hand, or is ISM just an odd device? I would say that ISM is definitely a special-case device, even just looking at the way it's implemented in the base kernel (interacting directly with the s390 kernel PCI layer in order to avoid use of MIO instructions -- no other driver does this). But that said, having the two requirements hand-in-hand I think is not bad, though -- This approach ensures the specific instruction the guest wanted (or in this case, needed) is actually executed on the underlying host. That said, the ability to re-use the large write for other devices would be nice -- but as hinted in the QEMU cover letter, this approach only works because ISM does not support MSI-X; using this approach for MSI-X-enabled devices breaks the MSI-X masking that vfio-pci does in QEMU (I tried an approach that used this region approach for all 3 instructions as a test, PCISTG/PCISTB/PCILG, and threw it against mlx -- any writes against an MSI-X enabled bar will miss the msi-x notifiers since we aren't performing memory operations against the typical vfio-pci bar). > > If there's an expectation that the new region will always use the > non-MIO instructions (in addition to the changed write handling), it > should be noted in the description for the region as well. > Yes, this is indeed the expectation; I can clarify that.
On 12/11/20 10:01 AM, Matthew Rosato wrote: > On 12/11/20 9:35 AM, Cornelia Huck wrote: >> On Thu, 10 Dec 2020 10:51:23 -0500 >> Matthew Rosato <mjrosato@linux.ibm.com> wrote: >> >>> On 12/10/20 7:33 AM, Cornelia Huck wrote: >>>> On Wed, 9 Dec 2020 15:27:46 -0500 >>>> Matthew Rosato <mjrosato@linux.ibm.com> wrote: >>>>> Today, ISM devices are completely disallowed for vfio-pci >>>>> passthrough as >>>>> QEMU will reject the device due to an (inappropriate) MSI-X check. >>>>> However, in an effort to enable ISM device passthrough, I realized >>>>> that the >>>>> manner in which ISM performs block write operations is highly >>>>> incompatible >>>>> with the way that QEMU s390 PCI instruction interception and >>>>> vfio_pci_bar_rw break up I/O operations into 8B and 4B operations >>>>> -- ISM >>>>> devices have particular requirements in regards to the alignment, >>>>> size and >>>>> order of writes performed. Furthermore, they require that >>>>> legacy/non-MIO >>>>> s390 PCI instructions are used, which is also not guaranteed when >>>>> the I/O >>>>> is passed through the typical userspace channels. >>>> >>>> The part about the non-MIO instructions confuses me. How can MIO >>>> instructions be generated with the current code, and why does changing >>> >>> So to be clear, they are not being generated at all in the guest as the >>> necessary facility is reported as unavailable. >>> >>> Let's talk about Linux in LPAR / the host kernel: When hardware that >>> supports MIO instructions is available, all userspace I/O traffic is >>> going to be routed through the MIO variants of the s390 PCI >>> instructions. This is working well for other device types, but does not >>> work for ISM which does not support these variants. However, the ISM >>> driver also does not invoke the userspace I/O routines for the kernel, >>> it invokes the s390 PCI layer directly, which in turn ensures the proper >>> PCI instructions are used -- This approach falls apart when the guest >>> ISM driver invokes those routines in the guest -- we (qemu) pass those >>> non-MIO instructions from the guest as memory operations through >>> vfio-pci, traversing through the vfio I/O layer in the guest >>> (vfio_pci_bar_rw and friends), where we then arrive in the host s390 PCI >>> layer -- where the MIO variant is used because the facility is >>> available. >>> >>> Per conversations with Niklas (on CC), it's not trivial to decide by the >>> time we reach the s390 PCI I/O layer to switch gears and use the non-MIO >>> instruction set. >>> >>>> the write pattern help? >>> >>> The write pattern is a separate issue from non-MIO instruction >>> requirements... Certain address spaces require specific instructions to >>> be used (so, no substituting PCISTG for PCISTB - that happens too by >>> default for any writes coming into the host s390 PCI layer that are >>> <=8B, and they all are when the PCISTB is broken up into 8B memory >>> operations that travel through vfio_pci_bar_rw, which further breaks >>> those up into 4B operations). There's also a requirement for some >>> writes that the data, if broken up, be written in a certain order in >>> order to properly trigger events. :( The ability to pass the entire >>> PCISTB payload vs breaking it into 8B chunks is also significantly >>> faster. >> >> Let me summarize this to make sure I understand this new region >> correctly: >> >> - some devices may have relaxed alignment/length requirements for >> pcistb (and friends?) > > The relaxed alignment bit is really specific to PCISTB behavior, so the > "and friends" doesn't apply there. > >> - some devices may actually require writes to be done in a large chunk >> instead of being broken up (is that a strict subset of the devices >> above?) > > Yes, this is specific to ISM devices, which are always a relaxed > alignment/length device. > > The inverse is an interesting question though (relaxed alignment devices > that are not ISM, which you've posed as a possible future extension for > emulated devices). I'm not sure that any (real devices) exist where > (relaxed_alignment && !ism), but 'what if' -- I guess the right approach > would mean additional code in QEMU to handle relaxed alignment for the > vfio mmio path as well (seen as pcistb_default in my qemu patchset) and > being very specific in QEMU to only enable the region for an ism device. Let me be more precise there... It would be additional code to handle relaxed alignment for the default pcistb path (pcistb_default) which would include BOTH emulated devices (should we ever surface the relaxed alignment CLP bit and the guest kernel honor it) as well as any s390x vfio-pci device that doesn't use this new I/O region described here. > >> - some devices do not support the new MIO instructions (is that a >> subset of the relaxed alignment devices? I'm not familiar with the >> MIO instructions) >> > > The non-MIO requirement is again specific to ISM, which is a subset of > the relaxed alignment devices. In this case, the requirement is not > limited to PCISTB, and that's why PCILG is also included here. The ISM > driver does not use PCISTG, and the only PCISTG instructions coming from > the guest against an ISM device would be against the config space and > those are OK to go through vfio still; so what was provided via the > region is effectively the bare-minimum requirement to allow ISM to > function properly in the guest. > >> The patchsets introduce a new region that (a) is used by QEMU to submit >> writes in one go, and (b) makes sure to call into the non-MIO >> instructions directly; it's basically killing two birds with one stone >> for ISM devices. Are these two requirements (large writes and non-MIO) >> always going hand-in-hand, or is ISM just an odd device? > > I would say that ISM is definitely a special-case device, even just > looking at the way it's implemented in the base kernel (interacting > directly with the s390 kernel PCI layer in order to avoid use of MIO > instructions -- no other driver does this). But that said, having the > two requirements hand-in-hand I think is not bad, though -- This > approach ensures the specific instruction the guest wanted (or in this > case, needed) is actually executed on the underlying host. > > That said, the ability to re-use the large write for other devices would > be nice -- but as hinted in the QEMU cover letter, this approach only > works because ISM does not support MSI-X; using this approach for > MSI-X-enabled devices breaks the MSI-X masking that vfio-pci does in > QEMU (I tried an approach that used this region approach for all 3 > instructions as a test, PCISTG/PCISTB/PCILG, and threw it against mlx -- > any writes against an MSI-X enabled bar will miss the msi-x notifiers > since we aren't performing memory operations against the typical > vfio-pci bar). > >> >> If there's an expectation that the new region will always use the >> non-MIO instructions (in addition to the changed write handling), it >> should be noted in the description for the region as well. >> > > Yes, this is indeed the expectation; I can clarify that. >
On Fri, 11 Dec 2020 10:04:43 -0500 Matthew Rosato <mjrosato@linux.ibm.com> wrote: > On 12/11/20 10:01 AM, Matthew Rosato wrote: > > On 12/11/20 9:35 AM, Cornelia Huck wrote: > >> Let me summarize this to make sure I understand this new region > >> correctly: > >> > >> - some devices may have relaxed alignment/length requirements for > >> pcistb (and friends?) > > > > The relaxed alignment bit is really specific to PCISTB behavior, so the > > "and friends" doesn't apply there. Ok. > > > >> - some devices may actually require writes to be done in a large chunk > >> instead of being broken up (is that a strict subset of the devices > >> above?) > > > > Yes, this is specific to ISM devices, which are always a relaxed > > alignment/length device. > > > > The inverse is an interesting question though (relaxed alignment devices > > that are not ISM, which you've posed as a possible future extension for > > emulated devices). I'm not sure that any (real devices) exist where > > (relaxed_alignment && !ism), but 'what if' -- I guess the right approach > > would mean additional code in QEMU to handle relaxed alignment for the > > vfio mmio path as well (seen as pcistb_default in my qemu patchset) and > > being very specific in QEMU to only enable the region for an ism device. > > Let me be more precise there... It would be additional code to handle > relaxed alignment for the default pcistb path (pcistb_default) which > would include BOTH emulated devices (should we ever surface the relaxed > alignment CLP bit and the guest kernel honor it) as well as any s390x > vfio-pci device that doesn't use this new I/O region described here. Understood. Not sure if it is useful, but the important part is that we could extend it if we wanted. > > > > >> - some devices do not support the new MIO instructions (is that a > >> subset of the relaxed alignment devices? I'm not familiar with the > >> MIO instructions) > >> > > > > The non-MIO requirement is again specific to ISM, which is a subset of > > the relaxed alignment devices. In this case, the requirement is not > > limited to PCISTB, and that's why PCILG is also included here. The ISM > > driver does not use PCISTG, and the only PCISTG instructions coming from > > the guest against an ISM device would be against the config space and > > those are OK to go through vfio still; so what was provided via the > > region is effectively the bare-minimum requirement to allow ISM to > > function properly in the guest. > > > >> The patchsets introduce a new region that (a) is used by QEMU to submit > >> writes in one go, and (b) makes sure to call into the non-MIO > >> instructions directly; it's basically killing two birds with one stone > >> for ISM devices. Are these two requirements (large writes and non-MIO) > >> always going hand-in-hand, or is ISM just an odd device? > > > > I would say that ISM is definitely a special-case device, even just > > looking at the way it's implemented in the base kernel (interacting > > directly with the s390 kernel PCI layer in order to avoid use of MIO > > instructions -- no other driver does this). But that said, having the > > two requirements hand-in-hand I think is not bad, though -- This > > approach ensures the specific instruction the guest wanted (or in this > > case, needed) is actually executed on the underlying host. The basic question I have is whether it makes sense to specialcase the ISM device (can we even find out that we're dealing with an ISM device here?) to force the non-MIO instructions, as it is just a device with some special requirements, or tie non-MIO to relaxed alignment. (Could relaxed alignment devices in theory be served by MIO instructions as well?) Another thing that came to my mind is whether we consider the guest to be using a pci device and needing weird instructions to do that because it's on s390, or whether it is issuing instructions for a device that happens to be a pci device (sorry if that sounds a bit meta :) > > > > That said, the ability to re-use the large write for other devices would > > be nice -- but as hinted in the QEMU cover letter, this approach only > > works because ISM does not support MSI-X; using this approach for > > MSI-X-enabled devices breaks the MSI-X masking that vfio-pci does in > > QEMU (I tried an approach that used this region approach for all 3 > > instructions as a test, PCISTG/PCISTB/PCILG, and threw it against mlx -- > > any writes against an MSI-X enabled bar will miss the msi-x notifiers > > since we aren't performing memory operations against the typical > > vfio-pci bar). Ugh. I wonder why ISM is so different from anything else. > > > >> > >> If there's an expectation that the new region will always use the > >> non-MIO instructions (in addition to the changed write handling), it > >> should be noted in the description for the region as well. > >> > > > > Yes, this is indeed the expectation; I can clarify that. > > Thanks!
On 12/17/20 7:59 AM, Cornelia Huck wrote: > On Fri, 11 Dec 2020 10:04:43 -0500 > Matthew Rosato <mjrosato@linux.ibm.com> wrote: > >> On 12/11/20 10:01 AM, Matthew Rosato wrote: >>> On 12/11/20 9:35 AM, Cornelia Huck wrote: > >>>> Let me summarize this to make sure I understand this new region >>>> correctly: >>>> >>>> - some devices may have relaxed alignment/length requirements for >>>> pcistb (and friends?) >>> >>> The relaxed alignment bit is really specific to PCISTB behavior, so the >>> "and friends" doesn't apply there. > > Ok. > >>> >>>> - some devices may actually require writes to be done in a large chunk >>>> instead of being broken up (is that a strict subset of the devices >>>> above?) >>> >>> Yes, this is specific to ISM devices, which are always a relaxed >>> alignment/length device. >>> >>> The inverse is an interesting question though (relaxed alignment devices >>> that are not ISM, which you've posed as a possible future extension for >>> emulated devices). I'm not sure that any (real devices) exist where >>> (relaxed_alignment && !ism), but 'what if' -- I guess the right approach >>> would mean additional code in QEMU to handle relaxed alignment for the >>> vfio mmio path as well (seen as pcistb_default in my qemu patchset) and >>> being very specific in QEMU to only enable the region for an ism device. >> >> Let me be more precise there... It would be additional code to handle >> relaxed alignment for the default pcistb path (pcistb_default) which >> would include BOTH emulated devices (should we ever surface the relaxed >> alignment CLP bit and the guest kernel honor it) as well as any s390x >> vfio-pci device that doesn't use this new I/O region described here. > > Understood. Not sure if it is useful, but the important part is that we > could extend it if we wanted. > >> >>> >>>> - some devices do not support the new MIO instructions (is that a >>>> subset of the relaxed alignment devices? I'm not familiar with the >>>> MIO instructions) >>>> >>> >>> The non-MIO requirement is again specific to ISM, which is a subset of >>> the relaxed alignment devices. In this case, the requirement is not >>> limited to PCISTB, and that's why PCILG is also included here. The ISM >>> driver does not use PCISTG, and the only PCISTG instructions coming from >>> the guest against an ISM device would be against the config space and >>> those are OK to go through vfio still; so what was provided via the >>> region is effectively the bare-minimum requirement to allow ISM to >>> function properly in the guest. >>> >>>> The patchsets introduce a new region that (a) is used by QEMU to submit >>>> writes in one go, and (b) makes sure to call into the non-MIO >>>> instructions directly; it's basically killing two birds with one stone >>>> for ISM devices. Are these two requirements (large writes and non-MIO) >>>> always going hand-in-hand, or is ISM just an odd device? >>> >>> I would say that ISM is definitely a special-case device, even just >>> looking at the way it's implemented in the base kernel (interacting >>> directly with the s390 kernel PCI layer in order to avoid use of MIO >>> instructions -- no other driver does this). But that said, having the >>> two requirements hand-in-hand I think is not bad, though -- This >>> approach ensures the specific instruction the guest wanted (or in this >>> case, needed) is actually executed on the underlying host. > > The basic question I have is whether it makes sense to specialcase the > ISM device (can we even find out that we're dealing with an ISM device > here?) to force the non-MIO instructions, as it is just a device with Yes, with the addition of the CLP data passed from the host via vfio capabilities, we can tell this is an ISM device specifically via the 'pft' field in VFOI_DEVICE_INFO_CAP_ZPCI_BASE. We don't actually surface that field to the guest itself in the Q PCI FN clp rsponse (has to do with Function Measurement Block requirements) but we can certainly use that information in QEMU to restrict this behavior to only ISM devices. > some special requirements, or tie non-MIO to relaxed alignment. (Could > relaxed alignment devices in theory be served by MIO instructions as > well?) In practice, I think there are none today, but per the architecture it IS possible to have relaxed alignment devices served by MIO instructions, so we shouldn't rely on that bit alone as I'm doing in this RFC. I think instead relying on the pft value as I mention above is what we have to do. > > Another thing that came to my mind is whether we consider the guest to > be using a pci device and needing weird instructions to do that because > it's on s390, or whether it is issuing instructions for a device that > happens to be a pci device (sorry if that sounds a bit meta :) > Typically, I'd classify things as the former but I think ISM seems more like the latter -- To me, ISM seems like less a classic PCI device and more a device that happens to be using s390 PCI interfaces to accomplish its goal. But it's probably more of a case of this particular device (and it's driver) are s390-specific and therefore built with the unique s390 interface in-mind (and in fact invokes it directly rather than through the general PCI layer), rather than fitting the typical PCI device architecture on top of the s390 interface. >>> >>> That said, the ability to re-use the large write for other devices would >>> be nice -- but as hinted in the QEMU cover letter, this approach only >>> works because ISM does not support MSI-X; using this approach for >>> MSI-X-enabled devices breaks the MSI-X masking that vfio-pci does in >>> QEMU (I tried an approach that used this region approach for all 3 >>> instructions as a test, PCISTG/PCISTB/PCILG, and threw it against mlx -- >>> any writes against an MSI-X enabled bar will miss the msi-x notifiers >>> since we aren't performing memory operations against the typical >>> vfio-pci bar). > > Ugh. I wonder why ISM is so different from anything else. > ... I've asked myself that alot lately :) >>> >>>> >>>> If there's an expectation that the new region will always use the >>>> non-MIO instructions (in addition to the changed write handling), it >>>> should be noted in the description for the region as well. >>>> >>> >>> Yes, this is indeed the expectation; I can clarify that. >>> > > Thanks! >
On Thu, 17 Dec 2020 11:04:48 -0500 Matthew Rosato <mjrosato@linux.ibm.com> wrote: > On 12/17/20 7:59 AM, Cornelia Huck wrote: > > The basic question I have is whether it makes sense to specialcase the > > ISM device (can we even find out that we're dealing with an ISM device > > here?) to force the non-MIO instructions, as it is just a device with > > Yes, with the addition of the CLP data passed from the host via vfio > capabilities, we can tell this is an ISM device specifically via the > 'pft' field in VFOI_DEVICE_INFO_CAP_ZPCI_BASE. We don't actually > surface that field to the guest itself in the Q PCI FN clp rsponse (has > to do with Function Measurement Block requirements) but we can certainly > use that information in QEMU to restrict this behavior to only ISM devices. > > > some special requirements, or tie non-MIO to relaxed alignment. (Could > > relaxed alignment devices in theory be served by MIO instructions as > > well?) > > In practice, I think there are none today, but per the architecture it > IS possible to have relaxed alignment devices served by MIO > instructions, so we shouldn't rely on that bit alone as I'm doing in > this RFC. I think instead relying on the pft value as I mention above > is what we have to do. From what you write this looks like the best way to me as well. > > > > > Another thing that came to my mind is whether we consider the guest to > > be using a pci device and needing weird instructions to do that because > > it's on s390, or whether it is issuing instructions for a device that > > happens to be a pci device (sorry if that sounds a bit meta :) > > > > Typically, I'd classify things as the former but I think ISM seems more > like the latter -- To me, ISM seems like less a classic PCI device and > more a device that happens to be using s390 PCI interfaces to accomplish > its goal. But it's probably more of a case of this particular device > (and it's driver) are s390-specific and therefore built with the unique > s390 interface in-mind (and in fact invokes it directly rather than > through the general PCI layer), rather than fitting the typical PCI > device architecture on top of the s390 interface. Nod, it certainly feels like that.