From patchwork Mon Nov 5 14:36:12 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Marc Zyngier X-Patchwork-Id: 10668357 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 1FB6D17D4 for ; Mon, 5 Nov 2018 14:36:51 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 0B1DD29727 for ; Mon, 5 Nov 2018 14:36:51 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id EF22029907; Mon, 5 Nov 2018 14:36:50 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-7.9 required=2.0 tests=BAYES_00,MAILING_LIST_MULTI, RCVD_IN_DNSWL_HI autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 6D9F729727 for ; Mon, 5 Nov 2018 14:36:50 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729585AbeKEX4t (ORCPT ); Mon, 5 Nov 2018 18:56:49 -0500 Received: from usa-sjc-mx-foss1.foss.arm.com ([217.140.101.70]:44888 "EHLO foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726255AbeKEX4t (ORCPT ); Mon, 5 Nov 2018 18:56:49 -0500 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id E4924A78; Mon, 5 Nov 2018 06:36:48 -0800 (PST) Received: from filthy-habits.cambridge.arm.com (filthy-habits.cambridge.arm.com [10.1.196.62]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 6B1F23F944; Mon, 5 Nov 2018 06:36:47 -0800 (PST) From: Marc Zyngier To: linux-arm-kernel@lists.infradead.org, kvmarm@lists.cs.columbia.edu, kvm@vger.kernel.org Cc: Will Deacon , Catalin Marinas , Christoffer Dall , Mark Rutland , Suzuki K Poulose Subject: [PATCH 0/4] Workaround for Cortex-A76 erratum 1165522 Date: Mon, 5 Nov 2018 14:36:12 +0000 Message-Id: <20181105143617.120602-1-marc.zyngier@arm.com> X-Mailer: git-send-email 2.19.1 MIME-Version: 1.0 Sender: kvm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Early Cortex-A76 suffer from an erratum that can result in invalid TLBs when the CPU speculatively executes an AT instruction in the middle of a guest world switch, while the guest virtual memory configuration is in an inconsistent state. We handle this issue by mandating the use of VHE and making sure that the guest context is fully installed before switching HCR_EL2.TGE to zero. This ensures that a speculated AT instruction is either executed on the host context (TGE set) or the guest context (TGE clear), and that there is no intermediate state. Marc Zyngier (4): KVM: arm64: Rework detection of SVE, !VHE systems KVM: arm64: Allow implementations to be confined to using VHE arm64: KVM: Install stage-2 translation before enabling traps on VHE arm64: KVM: Implement workaround for Cortex-A76 erratum 1165522 Documentation/arm64/silicon-errata.txt | 1 + arch/arm/include/asm/kvm_host.h | 3 ++- arch/arm64/Kconfig | 12 ++++++++++++ arch/arm64/include/asm/cpucaps.h | 3 ++- arch/arm64/include/asm/kvm_host.h | 14 ++++++++++---- arch/arm64/include/asm/kvm_hyp.h | 6 ++++++ arch/arm64/kernel/cpu_errata.c | 8 ++++++++ arch/arm64/kvm/hyp/switch.c | 16 +++++++++++++++- virt/kvm/arm/arm.c | 17 ++++++++++++----- 9 files changed, 68 insertions(+), 12 deletions(-)