From patchwork Thu Aug 27 09:21:23 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yifei Jiang X-Patchwork-Id: 11740309 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 8578D739 for ; Thu, 27 Aug 2020 09:22:41 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 770A62177B for ; Thu, 27 Aug 2020 09:22:41 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728369AbgH0JWk (ORCPT ); Thu, 27 Aug 2020 05:22:40 -0400 Received: from szxga05-in.huawei.com ([45.249.212.191]:10272 "EHLO huawei.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1728228AbgH0JWh (ORCPT ); Thu, 27 Aug 2020 05:22:37 -0400 Received: from DGGEMS402-HUB.china.huawei.com (unknown [172.30.72.59]) by Forcepoint Email with ESMTP id D58A74862EF1E1423524; Thu, 27 Aug 2020 17:22:34 +0800 (CST) Received: from huawei.com (10.174.187.31) by DGGEMS402-HUB.china.huawei.com (10.3.19.202) with Microsoft SMTP Server id 14.3.487.0; Thu, 27 Aug 2020 17:22:25 +0800 From: Yifei Jiang To: , CC: , , , , , , , , , , , , , Yifei Jiang Subject: [PATCH RFC v3 00/14] Add riscv kvm accel support Date: Thu, 27 Aug 2020 17:21:23 +0800 Message-ID: <20200827092137.479-1-jiangyifei@huawei.com> X-Mailer: git-send-email 2.26.2.windows.1 MIME-Version: 1.0 X-Originating-IP: [10.174.187.31] X-CFilter-Loop: Reflected Sender: kvm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org This series adds both riscv32 and riscv64 kvm support, and implements migration based on riscv. It is based on temporarily unaccepted kvm: https://github.com/kvm-riscv/linux Compared to RFC v2, the migration is supported in this series. The new added migration feature also requires the following patches: [1] [PATCH RFC 0/2] Add log dirty support https://www.mail-archive.com/linux-kernel@vger.kernel.org/msg2284945.html [2] [PATCH] target/riscv: raise exception to HS-mode at get_physical_address https://patchew.org/QEMU/20200824084158.1769-1-jiangyifei@huawei.com/ Several steps to use this: 1. Build emulation $ ./configure --target-list=riscv64-softmmu $ make -j$(nproc) 2. Build kernel https://github.com/kvm-riscv/linux 3. Build QEMU VM I cross built in riscv toolchain. $ PKG_CONFIG_LIBDIR= $ export PKG_CONFIG_SYSROOT_DIR= $ ./configure --target-list=riscv64-softmmu --enable-kvm \ --cross-prefix=riscv64-linux-gnu- --disable-libiscsi --disable-glusterfs \ --disable-libusb --disable-usb-redir --audio-drv-list= --disable-opengl \ --disable-libxml2 $ make -j$(nproc) 4. Start emulation $ ./qemu-system-riscv64 -M virt -m 4096M -cpu rv64,x-h=true -nographic \ -name guest=riscv-hyp,debug-threads=on \ -smp 4 \ -bios ./fw_jump.bin \ -kernel ./Image \ -drive file=./hyp.img,format=raw,id=hd0 \ -device virtio-blk-device,drive=hd0 \ -append "root=/dev/vda rw console=ttyS0 earlycon=sbi" 5. Start kvm-acceled QEMU VM in emulation $ ./qemu-system-riscv64 -M virt,accel=kvm -m 1024M -cpu host -nographic \ -name guest=riscv-guset \ -smp 2 \ -bios none \ -kernel ./Image \ -drive file=./guest.img,format=raw,id=hd0 \ -device virtio-blk-device,drive=hd0 \ -append "root=/dev/vda rw console=ttyS0 earlycon=sbi" This following link describes the details about live migration steps: https://gitee.com/openeuler/qemu/wikis/Live%20migration?sort_id=2767831 Changes since RFC v2 1. Fix checkpatch error at target/riscv/sbi_ecall_interface.h. 2. Add riscv migration support. Changes since RFC v1 1. Add separate SBI ecall interface header. 2. Add riscv32 kvm accel support. Yifei Jiang (14): linux-header: Update linux/kvm.h target/riscv: Add target/riscv/kvm.c to place the public kvm interface target/riscv: Implement function kvm_arch_init_vcpu target/riscv: Implement kvm_arch_get_registers arget/riscv: Implement kvm_arch_put_registers target/riscv: Support start kernel directly by KVM hw/riscv: PLIC update external interrupt by KVM when kvm enabled target/riscv: Handler KVM_EXIT_RISCV_SBI exit target/riscv: Add host cpu type target/riscv: Add sifive_plic vmstate target/riscv: Support riscv cpu vmstate target/riscv: Add kvm_riscv_get/put_regs_timer target/riscv: Implement virtual time adjusting with vm state changing target/riscv: Support virtual time context synchronization configure | 1 + hw/riscv/sifive_plic.c | 55 ++- hw/riscv/virt.c | 8 + include/hw/riscv/sifive_plic.h | 1 + linux-headers/linux/kvm.h | 8 + target/riscv/cpu.c | 41 +- target/riscv/cpu.h | 10 + target/riscv/kvm.c | 599 +++++++++++++++++++++++++++++ target/riscv/kvm_riscv.h | 25 ++ target/riscv/meson.build | 1 + target/riscv/sbi_ecall_interface.h | 72 ++++ 11 files changed, 809 insertions(+), 12 deletions(-) create mode 100644 target/riscv/kvm.c create mode 100644 target/riscv/kvm_riscv.h create mode 100644 target/riscv/sbi_ecall_interface.h