From patchwork Thu Apr 22 09:34:34 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yang Zhong X-Patchwork-Id: 12218147 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-11.8 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE, SPF_PASS,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 12E66C433ED for ; Thu, 22 Apr 2021 10:05:34 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id C216661360 for ; Thu, 22 Apr 2021 10:05:33 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235755AbhDVKGH (ORCPT ); Thu, 22 Apr 2021 06:06:07 -0400 Received: from mga04.intel.com ([192.55.52.120]:61845 "EHLO mga04.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230365AbhDVKGH (ORCPT ); Thu, 22 Apr 2021 06:06:07 -0400 IronPort-SDR: Ia94LpGtsiDT0kOxB8/UcjG4zHMPsIqwisy7b7lP0ujPVOmoLNZHgs4d61xfE4LCLDDK9bOEwj EEr9XbdjaRKA== X-IronPort-AV: E=McAfee;i="6200,9189,9961"; a="193741589" X-IronPort-AV: E=Sophos;i="5.82,242,1613462400"; d="scan'208";a="193741589" Received: from fmsmga008.fm.intel.com ([10.253.24.58]) by fmsmga104.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 22 Apr 2021 03:05:32 -0700 IronPort-SDR: vU0Siz1iLObUsc/WZqlp80/j2Jo2IwJwF6jN2WgiPdpgjworQrGkWDAWaJws5ZAM9Q9wjUI0Pr vPFRONUyKh8Q== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.82,242,1613462400"; d="scan'208";a="421317100" Received: from icx-2s.bj.intel.com ([10.240.192.119]) by fmsmga008.fm.intel.com with ESMTP; 22 Apr 2021 03:05:31 -0700 From: Yang Zhong To: kvm@vger.kernel.org Cc: pbonzini@redhat.com, seanjc@google.com, yang.zhong@intel.com Subject: [PATCH 0/2] Cleanup the registers read/write access Date: Thu, 22 Apr 2021 17:34:34 +0800 Message-Id: <20210422093436.78683-1-yang.zhong@intel.com> X-Mailer: git-send-email 2.29.2.334.gfaefdd61ec MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org The KVM has defined the GP registers and pointer register access methods in the ./arch/x86/kvm/kvm_cache_regs.h file, but there are still some GP and pointer registers access using older style. We should keep those registers access consistent in vmx and svm. Yang Zhong (2): KVM: VMX: Keep registers read/write consistent with definition KVM: SVM: Keep registers read/write consistent with definition arch/x86/kvm/svm/nested.c | 2 +- arch/x86/kvm/svm/sev.c | 65 ++++++++++++++++++++------------------- arch/x86/kvm/svm/svm.c | 20 ++++++------ arch/x86/kvm/vmx/vmx.c | 11 ++++--- 4 files changed, 50 insertions(+), 48 deletions(-)