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[v3,0/5] KVM: x86/pmu: Add support to enable guest PEBS via PT

Message ID 20210512084446.342526-1-like.xu@linux.intel.com (mailing list archive)
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Series KVM: x86/pmu: Add support to enable guest PEBS via PT | expand


Like Xu May 12, 2021, 8:44 a.m. UTC
I recently noticed that some developers particularly like the PT feature.
So please help review this version since a new kernel cycle has begun .

Intel new hardware (Atom processors based on the Tremont microarchitecture)
introduces some Processor Event-Based Sampling (PEBS) extensions that output
the PEBS record to Intel PT stream instead of DS area. The PEBS record will
be packaged in a specific format when outputting to Intel PT buffer.

To use PEBS-via-PT, the guest driver will firstly check the basic support
for PEBS-via-DS, so this patch set is based on the PEBS-via-DS enabling
patch set [1].

We can use PEBS-via-PT feature on the Linux guest like native:
(you may need modprobe kvm-intel.ko with pt_mode=1)

Recording is selected by using the aux-output config term e.g.
$ perf record -c 10000 -e '{intel_pt/branch=0/,cycles/aux-output/ppp}' uname
Intel Processor Trace: TSC not available
[ perf record: Woken up 1 times to write data ]
[ perf record: Captured and wrote 0.028 MB perf.data ]

To display PEBS events from the Intel PT trace, use the itrace 'o' option e.g.
$ perf script --itrace=oe
uname   853   113.230292:      10000 cycles/aux-output/ppp:  ffffffff8125dcd9 perf_output_begin+0x29 ([kernel.kallsyms])
uname   853   113.230443:      10000 cycles/aux-output/ppp:  ffffffff8106de86 native_write_msr+0x6 ([kernel.kallsyms])
uname   853   113.230444:      10000 cycles/aux-output/ppp:  ffffffff81bd035b exc_nmi+0x10b ([kernel.kallsyms])
uname   853   113.230567:      10000 cycles/aux-output/ppp:  ffffffff8106de86 native_write_msr+0x6 ([kernel.kallsyms])
uname   853   113.230567:      10000 cycles/aux-output/ppp:  ffffffff8125dce0 perf_output_begin+0x30 ([kernel.kallsyms])
uname   853   113.230688:      10000 cycles/aux-output/ppp:  ffffffff8106de86 native_write_msr+0x6 ([kernel.kallsyms])
uname   853   113.230689:      10000 cycles/aux-output/ppp:  ffffffff81005da7 perf_event_nmi_handler+0x7 ([kernel.kallsyms])
uname   853   113.230816:      10000 cycles/aux-output/ppp:  ffffffff8106de86 native_write_msr+0x6 ([kernel.kallsyms])

Please check more details in each commit and feel free to comment.

V2 -> V3 Changelog:
- Add x86_pmu.pebs_vmx to ATOM_TREMONT and support PDIR counter;
- Rewrite get_gp_pmc() and get_fixed_pmc() based on PERF_CAP_PEBS_OUTPUT_PT;
- Check and add counter reload registers in the intel_guest_get_msrs();
- Expose this capability in the vmx_get_perf_capabilities();
[1] https://lore.kernel.org/kvm/20210511024214.280733-1-like.xu@linux.intel.com/

Like Xu (4):
  KVM: x86/pmu: Add pebs_vmx support for ATOM_TREMONT
  KVM: x86/pmu: Add counter reload MSR emulation for all counters
  KVM: x86/pmu: Add counter reload registers to the MSR-load list
  KVM: x86/pmu: Expose PEBS-via-PT in the KVM supported capabilities

Luwei Kang (1):
  KVM: x86/pmu: Add the base address parameter for get_fixed_pmc()

 arch/x86/events/intel/core.c     | 28 +++++++++++++++++++++++++
 arch/x86/events/perf_event.h     |  5 -----
 arch/x86/include/asm/kvm_host.h  |  1 +
 arch/x86/include/asm/msr-index.h |  6 ++++++
 arch/x86/kvm/pmu.c               |  5 ++---
 arch/x86/kvm/pmu.h               | 11 ++++++++--
 arch/x86/kvm/vmx/capabilities.h  |  5 ++++-
 arch/x86/kvm/vmx/pmu_intel.c     | 35 ++++++++++++++++++++++++++------
 arch/x86/kvm/vmx/vmx.h           |  2 +-
 9 files changed, 80 insertions(+), 18 deletions(-)