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Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB03.amd.com; Received: from SATLEXMB03.amd.com (165.204.84.17) by CO1NAM11FT015.mail.protection.outlook.com (10.13.175.130) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.4755.13 via Frontend Transport; Thu, 2 Dec 2021 23:59:16 +0000 Received: from sos-ubuntu2004-quartz01.amd.com (10.180.168.240) by SATLEXMB03.amd.com (10.181.40.144) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.17; Thu, 2 Dec 2021 17:59:13 -0600 From: Suravee Suthikulpanit To: , , CC: , , , , , , , , , , Suravee Suthikulpanit Subject: [PATCH v2 0/3] svm: avic: Allow AVIC support on system w/ physical APIC ID > 255 Date: Thu, 2 Dec 2021 17:58:22 -0600 Message-ID: <20211202235825.12562-1-suravee.suthikulpanit@amd.com> X-Mailer: git-send-email 2.25.1 MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB03.amd.com (10.181.40.144) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: ca913add-ba4a-46c7-cfea-08d9b5efbfd1 X-MS-TrafficTypeDiagnostic: DM5PR1201MB0121: X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:7219; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 02 Dec 2021 23:59:16.8008 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: ca913add-ba4a-46c7-cfea-08d9b5efbfd1 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB03.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CO1NAM11FT015.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM5PR1201MB0121 Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org Originally, AMD SVM AVIC supports 8-bit host physical APIC ID. However, newer AMD systems can have physical APIC ID larger than 255, and AVIC hardware has been extended to support upto the maximum physical APIC ID available in the system. This series introduces a helper function in the APIC subsystem to get the maximum physical APIC ID allowing the SVM AVIC driver to calculate the number of bits to program the host physical APIC ID in the AVIC physical APIC ID table entry. Regards, Suravee Suthikulpanit Changes from V1 (https://lkml.org/lkml/2021/11/10/243) : * Refactor AVIC hardware setup code into a helper function to simplify logic for enabling AVIC. (patch 1/3) * Simplify the logic in avic_init_host_physical_apicid_mask() by by removing the CPUID[0xb,0x1] check for processor level APIC ID mask. (patch 3/3) Suravee Suthikulpanit (3): KVM: SVM: Refactor AVIC hardware setup logic into helper function x86/apic: Add helper function to get maximum physical APIC ID KVM: SVM: Extend host physical APIC ID field to support more than 8-bit arch/x86/include/asm/apic.h | 1 + arch/x86/kernel/apic/apic.c | 6 ++++++ arch/x86/kvm/svm/avic.c | 38 +++++++++++++++++++++++++++++-------- arch/x86/kvm/svm/svm.c | 8 +------- arch/x86/kvm/svm/svm.h | 2 +- 5 files changed, 39 insertions(+), 16 deletions(-)