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Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; Received: from SATLEXMB04.amd.com (165.204.84.17) by DM6NAM11FT021.mail.protection.outlook.com (10.13.173.76) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.4951.12 via Frontend Transport; Wed, 2 Feb 2022 04:13:28 +0000 Received: from sp5-759chost.amd.com (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.18; Tue, 1 Feb 2022 22:13:26 -0600 From: Suravee Suthikulpanit To: , , CC: , , , , , , , , , , "Suravee Suthikulpanit" Subject: [PATCH v4 0/3] svm: avic: Allow AVIC support on system w/ physical APIC ID > 255 Date: Tue, 1 Feb 2022 22:11:09 -0600 Message-ID: <20220202041112.273017-1-suravee.suthikulpanit@amd.com> X-Mailer: git-send-email 2.25.1 MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB04.amd.com (10.181.40.145) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 2c79f930-c1d4-4ea6-d67d-08d9e6025df9 X-MS-TrafficTypeDiagnostic: BY5PR12MB3780:EE_ X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:7219; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 02 Feb 2022 04:13:28.9519 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 2c79f930-c1d4-4ea6-d67d-08d9e6025df9 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: DM6NAM11FT021.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BY5PR12MB3780 Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org Originally, AMD SVM AVIC supports 8-bit host physical APIC ID. However, newer AMD systems can have physical APIC ID larger than 255, and AVIC hardware has been extended to support upto 12-bit host physical APIC ID. This series introduces a helper function in the APIC subsystem to get the maximum physical APIC ID allowing the SVM AVIC driver to calculate the proper size to program the host physical APIC ID in the AVIC physical APIC ID table entry. Regards, Suravee Suthikulpanit Changes from V3 (https://lkml.org/lkml/2021/12/13/1062) * Rename and modify patch 1/3 to also set vcpu_(un)blocking only when AVIC is enabled. * PATCH 3/3: Instead of dynamically calculate the host physical APIC ID mask value, use the max host physical APIC ID to determine whether to use 8-bit or 12-bit mask. * PATCH 3/3: change avic_host_physical_id_mask size. * PATCH 3/3: change warning condition in avic_vcpu_load() Suravee Suthikulpanit (3): KVM: SVM: Only call vcpu_(un)blocking when AVIC is enabled. x86/apic: Add helper function to get maximum physical APIC ID KVM: SVM: Add support for 12-bit host physical APIC ID arch/x86/include/asm/apic.h | 1 + arch/x86/kernel/apic/apic.c | 6 +++++ arch/x86/kvm/svm/avic.c | 50 +++++++++++++++++++++++++++++-------- arch/x86/kvm/svm/svm.c | 10 ++------ arch/x86/kvm/svm/svm.h | 4 +-- 5 files changed, 49 insertions(+), 22 deletions(-)