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Tue, 12 Apr 2022 11:59:07 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 165.204.84.17) smtp.mailfrom=amd.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=amd.com; Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; Received: from SATLEXMB04.amd.com (165.204.84.17) by BN8NAM11FT032.mail.protection.outlook.com (10.13.177.88) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.5144.20 via Frontend Transport; Tue, 12 Apr 2022 11:59:07 +0000 Received: from sp5-759chost.amd.com (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.24; Tue, 12 Apr 2022 06:59:06 -0500 From: Suravee Suthikulpanit To: , CC: , , , , , , , Suravee Suthikulpanit Subject: [PATCH v2 00/12] Introducing AMD x2APIC Virtualization (x2AVIC) support Date: Tue, 12 Apr 2022 06:58:10 -0500 Message-ID: <20220412115822.14351-1-suravee.suthikulpanit@amd.com> X-Mailer: git-send-email 2.25.1 MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: b2168c21-0528-4cc9-44eb-08da1c7bd93b X-MS-TrafficTypeDiagnostic: SA0PR12MB4446:EE_ X-Microsoft-Antispam-PRVS: X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 12 Apr 2022 11:59:07.6816 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: b2168c21-0528-4cc9-44eb-08da1c7bd93b X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BN8NAM11FT032.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SA0PR12MB4446 Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org Previously, with AVIC, guest needs to disable x2APIC capability and can only run in APIC mode to activate hardware-accelerated interrupt virtualization. With x2AVIC, guest can run in x2APIC mode. This feature is indicated by the CPUID Fn8000_000A EDX[14], and it can be activated by setting bit 31 (enable AVIC) and bit 30 (x2APIC mode) of VMCB offset 60h. The mode of interrupt virtualization can dynamically change during runtime. For example, when AVIC is enabled, the hypervisor currently keeps track of the AVIC activation and set the VMCB bit 31 accordingly. With x2AVIC, the guest OS can also switch between APIC and x2APIC modes during runtime. The kvm_amd driver needs to also keep track and set the VMCB bit 30 accordingly. Besides, for x2AVIC, kvm_amd driver needs to disable interception for the x2APIC MSR range to allow AVIC hardware to virtualize register accesses. Testing: * This series has been tested booting a Linux VM with x2APIC physical and logical modes upto 512 vCPUs. Regards, Suravee Changes from v1 (https://lore.kernel.org/lkml/20220405230855.15376-1-suravee.suthikulpanit@amd.com/T/) * Rebase to v5.18 * Patch 7/12: remove logic to check for x2AVIC feature. Suravee Suthikulpanit (12): x86/cpufeatures: Introduce x2AVIC CPUID bit KVM: x86: lapic: Rename [GET/SET]_APIC_DEST_FIELD to [GET/SET]_XAPIC_DEST_FIELD KVM: SVM: Detect X2APIC virtualization (x2AVIC) support KVM: SVM: Update max number of vCPUs supported for x2AVIC mode KVM: SVM: Update avic_kick_target_vcpus to support 32-bit APIC ID KVM: SVM: Do not support updating APIC ID when in x2APIC mode KVM: SVM: Adding support for configuring x2APIC MSRs interception KVM: SVM: Update AVIC settings when changing APIC mode KVM: SVM: Introduce helper functions to (de)activate AVIC and x2AVIC KVM: SVM: Do not throw warning when calling avic_vcpu_load on a running vcpu KVM: SVM: Do not inhibit APICv when x2APIC is present kvm/x86: Remove APICV activate mode inconsistency check arch/x86/hyperv/hv_apic.c | 2 +- arch/x86/include/asm/apicdef.h | 4 +- arch/x86/include/asm/cpufeatures.h | 1 + arch/x86/include/asm/svm.h | 16 ++- arch/x86/kernel/apic/apic.c | 2 +- arch/x86/kernel/apic/ipi.c | 2 +- arch/x86/kvm/lapic.c | 2 +- arch/x86/kvm/svm/avic.c | 152 ++++++++++++++++++++++++++--- arch/x86/kvm/svm/svm.c | 55 ++++++----- arch/x86/kvm/svm/svm.h | 7 +- arch/x86/kvm/x86.c | 13 +-- 11 files changed, 204 insertions(+), 52 deletions(-)