| Message ID | 20220506033305.5135-1-weijiang.yang@intel.com (mailing list archive) |
|---|---|
| Headers | show |
| Series | Introduce Architectural LBR for vPMU | expand |
On 5/6/22 05:32, Yang Weijiang wrote: > [0] https://software.intel.com/sites/default/files/managed/c5/15/architecture-instruction-set-extensions-programming-reference.pdf > [1] https://lore.kernel.org/lkml/1593780569-62993-1-git-send-email-kan.liang@linux.intel.com/ > > Qemu patch: > https://patchwork.ozlabs.org/project/qemu-devel/cover/20220215195258.29149-1-weijiang.yang@intel.com/ > > Previous version: > v10: https://lore.kernel.org/all/20220422075509.353942-1-weijiang.yang@intel.com/ > > Changes in v11: > 1. Moved MSR_ARCH_LBR_DEPTH/CTL check code to a unified function.[Kan] > 2. Modified some commit messages per Kan's feedback. > 3. Rebased the patch series to 5.18-rc5. Thanks, this is mostly okay; the only remaining issues are Kan's feedback and saving/restoring on SMM enter/exit. The QEMU patches look good too. Paolo
On 5/10/2022 11:55 PM, Paolo Bonzini wrote: > On 5/6/22 05:32, Yang Weijiang wrote: >> [0] https://software.intel.com/sites/default/files/managed/c5/15/architecture-instruction-set-extensions-programming-reference.pdf >> [1] https://lore.kernel.org/lkml/1593780569-62993-1-git-send-email-kan.liang@linux.intel.com/ >> >> Qemu patch: >> https://patchwork.ozlabs.org/project/qemu-devel/cover/20220215195258.29149-1-weijiang.yang@intel.com/ >> >> Previous version: >> v10: https://lore.kernel.org/all/20220422075509.353942-1-weijiang.yang@intel.com/ >> >> Changes in v11: >> 1. Moved MSR_ARCH_LBR_DEPTH/CTL check code to a unified function.[Kan] >> 2. Modified some commit messages per Kan's feedback. >> 3. Rebased the patch series to 5.18-rc5. > Thanks, this is mostly okay; the only remaining issues are Kan's > feedback and saving/restoring on SMM enter/exit. Thanks Paolo, I'll fix Kan's feedback and the issue you mentioned in next version. > > The QEMU patches look good too. > > Paolo
Intel CPU model-specific LBR(Legacy LBR) evolved into Architectural LBR(Arch LBR[0]), it's the replacement of legacy LBR on new platforms. The native support patches were merged into 5.9 kernel tree, and this patch series is to enable Arch LBR in vPMU so that guest can benefit from the merits of the feature. The main advantages of Arch LBR are [1]: - Faster context switching due to XSAVES support and faster reset of LBR MSRs via the new DEPTH MSR - Faster LBR read for a non-PEBS event due to XSAVES support, which lowers the overhead of the NMI handler. - Linux kernel can support the LBR features without knowing the model number of the current CPU. From end user's point of view, the usage of Arch LBR is the same as the Legacy LBR that has been merged in the mainline. Note, in this series, we impose one restriction for guest Arch LBR: Guest can only set the same LBR record depth as host, this is due to the special behavior of MSR_ARCH_LBR_DEPTH: 1) On write to the MSR, it'll reset all Arch LBR recording MSRs to 0s. 2) XRSTORS resets all record MSRs to 0s if the saved depth mismatches MSR_ARCH_LBR_DEPTH. Enforcing the restriction keeps the KVM enabling patch simple and straightforward. [0] https://software.intel.com/sites/default/files/managed/c5/15/architecture-instruction-set-extensions-programming-reference.pdf [1] https://lore.kernel.org/lkml/1593780569-62993-1-git-send-email-kan.liang@linux.intel.com/ Qemu patch: https://patchwork.ozlabs.org/project/qemu-devel/cover/20220215195258.29149-1-weijiang.yang@intel.com/ Previous version: v10: https://lore.kernel.org/all/20220422075509.353942-1-weijiang.yang@intel.com/ Changes in v11: 1. Moved MSR_ARCH_LBR_DEPTH/CTL check code to a unified function.[Kan] 2. Modified some commit messages per Kan's feedback. 3. Rebased the patch series to 5.18-rc5. Like Xu (6): perf/x86/intel: Fix the comment about guest LBR support on KVM perf/x86/lbr: Simplify the exposure check for the LBR_INFO registers KVM: vmx/pmu: Emulate MSR_ARCH_LBR_DEPTH for guest Arch LBR KVM: vmx/pmu: Emulate MSR_ARCH_LBR_CTL for guest Arch LBR KVM: x86: Refine the matching and clearing logic for supported_xss KVM: x86: Add XSAVE Support for Architectural LBR Sean Christopherson (1): KVM: x86: Report XSS as an MSR to be saved if there are supported features Yang Weijiang (9): KVM: x86: Refresh CPUID on writes to MSR_IA32_XSS KVM: x86: Add Arch LBR MSRs to msrs_to_save_all list KVM: x86/pmu: Refactor code to support guest Arch LBR KVM: x86/vmx: Check Arch LBR config when return perf capabilities KVM: nVMX: Add necessary Arch LBR settings for nested VM KVM: x86/vmx: Clear Arch LBREn bit before inject #DB to guest KVM: x86/vmx: Flip Arch LBREn bit on guest state change KVM: x86: Add Arch LBR data MSR access interface KVM: x86/cpuid: Advertise Arch LBR feature in CPUID arch/x86/events/intel/core.c | 3 +- arch/x86/events/intel/lbr.c | 6 +- arch/x86/include/asm/kvm_host.h | 3 + arch/x86/include/asm/msr-index.h | 1 + arch/x86/include/asm/vmx.h | 4 + arch/x86/kvm/cpuid.c | 49 +++++++++- arch/x86/kvm/vmx/capabilities.h | 8 ++ arch/x86/kvm/vmx/nested.c | 7 +- arch/x86/kvm/vmx/pmu_intel.c | 157 ++++++++++++++++++++++++++++--- arch/x86/kvm/vmx/vmcs12.c | 1 + arch/x86/kvm/vmx/vmcs12.h | 3 +- arch/x86/kvm/vmx/vmx.c | 65 ++++++++++++- arch/x86/kvm/x86.c | 23 ++++- 13 files changed, 295 insertions(+), 35 deletions(-) base-commit: 672c0c5173427e6b3e2a9bbb7be51ceeec78093a