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Tue, 10 May 2022 09:02:20 +0000 Received: from drhqmail201.nvidia.com (10.126.190.180) by drhqmail203.nvidia.com (10.126.190.182) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.22; Tue, 10 May 2022 02:02:19 -0700 Received: from vdi.nvidia.com (10.127.8.10) by mail.nvidia.com (10.126.190.180) with Microsoft SMTP Server id 15.2.986.22 via Frontend Transport; Tue, 10 May 2022 02:02:16 -0700 From: Yishai Hadas To: , , CC: , , , , , , Subject: [PATCH V2 mlx5-next 0/4] Improve mlx5 live migration driver Date: Tue, 10 May 2022 12:02:02 +0300 Message-ID: <20220510090206.90374-1-yishaih@nvidia.com> X-Mailer: git-send-email 2.21.0 MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 5e5b21f7-0135-4629-377c-08da3263ca86 X-MS-TrafficTypeDiagnostic: MWHPR12MB1504:EE_ X-Microsoft-Antispam-PRVS: X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 10 May 2022 09:02:20.6041 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 5e5b21f7-0135-4629-377c-08da3263ca86 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[12.22.5.236];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CO1NAM11FT040.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MWHPR12MB1504 Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org This series improves mlx5 live migration driver in few aspects as of below. Refactor to enable running migration commands in parallel over the PF command interface. To achieve that we exposed from mlx5_core an API to let the VF be notified before that the PF command interface goes down/up. (e.g. PF reload upon health recovery). Once having the above functionality in place mlx5 vfio doesn't need any more to obtain the global PF lock upon using the command interface but can rely on the above mechanism to be in sync with the PF. This can enable parallel VFs migration over the PF command interface from kernel driver point of view. In addition, Moved to use the PF async command mode for the SAVE state command. This enables returning earlier to user space upon issuing successfully the command and improve latency by let things run in parallel. Alex, as this series touches mlx5_core we may need to send this in a pull request format to VFIO to avoid conflicts before acceptance. V2: - Improve packing in some structures as was suggested by Alex. - Move workqueue managing into set/remove migratable functions as was suggested by Alex. V1: https://lore.kernel.org/netdev/20220508131053.241347-1-yishaih@nvidia.com/ - Put the net/mlx5 patch as the first patch based on Jason's note. - Refactor and combine the previous first patch with the third patch to have a cleaner readable code, this follows Alex's notes on V0. V0: https://lore.kernel.org/netdev/20220504213309.GM49344@nvidia.com/T/ Yishai Yishai Hadas (4): net/mlx5: Expose mlx5_sriov_blocking_notifier_register / unregister APIs vfio/mlx5: Manage the VF attach/detach callback from the PF vfio/mlx5: Refactor to enable VFs migration in parallel vfio/mlx5: Run the SAVE state command in an async mode .../net/ethernet/mellanox/mlx5/core/sriov.c | 65 ++++- drivers/vfio/pci/mlx5/cmd.c | 236 +++++++++++++----- drivers/vfio/pci/mlx5/cmd.h | 52 +++- drivers/vfio/pci/mlx5/main.c | 122 ++++----- include/linux/mlx5/driver.h | 12 + 5 files changed, 351 insertions(+), 136 deletions(-) Reviewed-by: Alex Williamson