| Message ID | 20220602142620.3196-1-santosh.shukla@amd.com (mailing list archive) |
|---|---|
| Headers | show |
| Series | Virtual NMI feature | expand |
On Thu, Jun 2, 2022 at 7:26 AM Santosh Shukla <santosh.shukla@amd.com> wrote: > > Currently, NMI is delivered to the guest using the Event Injection > mechanism [1]. The Event Injection mechanism does not block the delivery > of subsequent NMIs. So the Hypervisor needs to track the NMI delivery > and its completion(by intercepting IRET) before sending a new NMI. > > Virtual NMI (VNMI) allows the hypervisor to inject the NMI into the guest > w/o using Event Injection mechanism meaning not required to track the > guest NMI and intercepting the IRET. To achieve that, > VNMI feature provides virtualized NMI and NMI_MASK capability bits in > VMCB intr_control - > V_NMI(11) - Indicates whether a virtual NMI is pending in the guest. > V_NMI_MASK(12) - Indicates whether virtual NMI is masked in the guest. > V_NMI_ENABLE(26) - Enables the NMI virtualization feature for the guest. > > When Hypervisor wants to inject NMI, it will set V_NMI bit, Processor will > clear the V_NMI bit and Set the V_NMI_MASK which means the Guest is > handling NMI, After the guest handled the NMI, The processor will clear > the V_NMI_MASK on the successful completion of IRET instruction > Or if VMEXIT occurs while delivering the virtual NMI. > > To enable the VNMI capability, Hypervisor need to program > V_NMI_ENABLE bit 1. > > The presence of this feature is indicated via the CPUID function > 0x8000000A_EDX[25]. > > Testing - > * Used qemu's `inject_nmi` for testing. > * tested with and w/o AVIC case. > * tested with kvm-unit-test > > Thanks, > Santosh > [1] https://www.amd.com/system/files/TechDocs/40332.pdf - APM Vol2, > ch-15.20 - "Event Injection". > > Santosh Shukla (7): > x86/cpu: Add CPUID feature bit for VNMI > KVM: SVM: Add VNMI bit definition > KVM: SVM: Add VNMI support in get/set_nmi_mask > KVM: SVM: Report NMI not allowed when Guest busy handling VNMI > KVM: SVM: Add VNMI support in inject_nmi > KVM: nSVM: implement nested VNMI > KVM: SVM: Enable VNMI feature > > arch/x86/include/asm/cpufeatures.h | 1 + > arch/x86/include/asm/svm.h | 7 +++++ > arch/x86/kvm/svm/nested.c | 8 +++++ > arch/x86/kvm/svm/svm.c | 47 ++++++++++++++++++++++++++++-- > arch/x86/kvm/svm/svm.h | 1 + > 5 files changed, 62 insertions(+), 2 deletions(-) > > -- > 2.25.1 When will we see vNMI support in silicon? Genoa? Where is this feature officially documented? Is there an AMD64 equivalent of the "Intel Architecture Instruction Set Extensions and Future Features" manual?
On 6/7/2022 4:31 AM, Jim Mattson wrote: > On Thu, Jun 2, 2022 at 7:26 AM Santosh Shukla <santosh.shukla@amd.com> wrote: >> >> Currently, NMI is delivered to the guest using the Event Injection >> mechanism [1]. The Event Injection mechanism does not block the delivery >> of subsequent NMIs. So the Hypervisor needs to track the NMI delivery >> and its completion(by intercepting IRET) before sending a new NMI. >> >> Virtual NMI (VNMI) allows the hypervisor to inject the NMI into the guest >> w/o using Event Injection mechanism meaning not required to track the >> guest NMI and intercepting the IRET. To achieve that, >> VNMI feature provides virtualized NMI and NMI_MASK capability bits in >> VMCB intr_control - >> V_NMI(11) - Indicates whether a virtual NMI is pending in the guest. >> V_NMI_MASK(12) - Indicates whether virtual NMI is masked in the guest. >> V_NMI_ENABLE(26) - Enables the NMI virtualization feature for the guest. >> >> When Hypervisor wants to inject NMI, it will set V_NMI bit, Processor will >> clear the V_NMI bit and Set the V_NMI_MASK which means the Guest is >> handling NMI, After the guest handled the NMI, The processor will clear >> the V_NMI_MASK on the successful completion of IRET instruction >> Or if VMEXIT occurs while delivering the virtual NMI. >> >> To enable the VNMI capability, Hypervisor need to program >> V_NMI_ENABLE bit 1. >> >> The presence of this feature is indicated via the CPUID function >> 0x8000000A_EDX[25]. >> >> Testing - >> * Used qemu's `inject_nmi` for testing. >> * tested with and w/o AVIC case. >> * tested with kvm-unit-test >> >> Thanks, >> Santosh >> [1] https://www.amd.com/system/files/TechDocs/40332.pdf >> ch-15.20 - "Event Injection". >> >> Santosh Shukla (7): >> x86/cpu: Add CPUID feature bit for VNMI >> KVM: SVM: Add VNMI bit definition >> KVM: SVM: Add VNMI support in get/set_nmi_mask >> KVM: SVM: Report NMI not allowed when Guest busy handling VNMI >> KVM: SVM: Add VNMI support in inject_nmi >> KVM: nSVM: implement nested VNMI >> KVM: SVM: Enable VNMI feature >> >> arch/x86/include/asm/cpufeatures.h | 1 + >> arch/x86/include/asm/svm.h | 7 +++++ >> arch/x86/kvm/svm/nested.c | 8 +++++ >> arch/x86/kvm/svm/svm.c | 47 ++++++++++++++++++++++++++++-- >> arch/x86/kvm/svm/svm.h | 1 + >> 5 files changed, 62 insertions(+), 2 deletions(-) >> >> -- >> 2.25.1 > > When will we see vNMI support in silicon? Genoa? > > Where is this feature officially documented? Is there an AMD64 > equivalent of the "Intel Architecture Instruction Set Extensions and > Future Features" manual? Hi Jim, A new revision of the Architecture programmers manual (APM) is slated to be release soon and that is going to have all the details for the above questions. Thanks, Santosh
On Wed, Jun 8, 2022 at 1:23 AM Shukla, Santosh <santosh.shukla@amd.com> wrote: > > > > On 6/7/2022 4:31 AM, Jim Mattson wrote: > > When will we see vNMI support in silicon? Genoa? > > > > Where is this feature officially documented? Is there an AMD64 > > equivalent of the "Intel Architecture Instruction Set Extensions and > > Future Features" manual? > > Hi Jim, > > A new revision of the Architecture programmers manual (APM) is slated > to be release soon and that is going to have all the details for > the above questions. It's been about 3 months, and I haven't seen the new APM yet. Is there an anticipated release date? It's hard to do a proper review of new features without documentation.