| Message ID | 20221111102645.82001-1-likexu@tencent.com (mailing list archive) |
|---|---|
| Headers | show |
| Series | KVM: x86: Add AMD Guest PerfMonV2 PMU support | expand |
Any comments to move it forward ? On 11/11/2022 6:26 pm, Like Xu wrote: > Starting with Zen4, core PMU on AMD platforms such as Genoa and > Ryzen-7000 will support PerfMonV2, and it is also compatible with > legacy PERFCTR_CORE behavior and msr addresses. > > If you don't have access to the hardware specification, the commits > d6d0c7f681fd..7685665c390d for host perf can also bring a quick > overview. Its main change is the addition of three msr's equivalent > to Intel V2, namely global_ctrl, global_status, global_status_clear. > > It is worth noting that this feature is very attractive for reducing the > overhead of PMU virtualization, since multiple msr accesses to multiple > counters will be replaced by a single access to the global register, > plus more accuracy gain when multiple guest counters are used. > > All related testcases are passed on a Genoa box. > Please feel free to run more tests, add more or share comments. > > Previous: > https://lore.kernel.org/kvm/20220919093453.71737-1-likexu@tencent.com/ > > V2 -> V3 Changelog: > - Renme pmc_is_enabled(); (Jim) > - Move the reprogram_counters() changes as a separate patch; (Jim) > - Refactoring to align with other set_msr() helper; (Sean) > - Fix the issue if userspace wants to expose v1 for whatever reason; (Sean) > - Add the feature flag X86_FEATURE_AMD_PMU_V2; (Sean) > - Check enable_pmu for intel 0xa as well; (Sean) > - Limit AMD pmu's KVM support to version 2 as well; > - Other nit changes around C code taste; (Sean) > > Like Xu (7): > KVM: x86/pmu: Rename pmc_is_enabled() to pmc_is_globally_enabled() > KVM: x86/pmu: Rewrite reprogram_counters() to improve performance > KVM: x86/pmu: Make part of the Intel v2 PMU MSRs handling x86 generic > KVM: x86/cpuid: Add X86_FEATURE_AMD_PMU_V2 as a KVM-only leaf entry > KVM: x86/svm/pmu: Add AMD PerfMonV2 support > KVM: x86/cpuid: Add AMD CPUID ExtPerfMonAndDbg leaf 0x80000022 > KVM: x86/cpuid: Use fast return for cpuid "0xa" leaf when !enable_pmu > > Sean Christopherson (1): > KVM: VMX: Refactor intel_pmu_set_msr() to align with other set_msr() > helpers > > arch/x86/include/asm/kvm-x86-pmu-ops.h | 1 - > arch/x86/include/asm/kvm_host.h | 1 + > arch/x86/kvm/cpuid.c | 32 ++++++- > arch/x86/kvm/pmu.c | 65 +++++++++++++-- > arch/x86/kvm/pmu.h | 28 ++++++- > arch/x86/kvm/reverse_cpuid.h | 10 +++ > arch/x86/kvm/svm/pmu.c | 73 +++++++++++----- > arch/x86/kvm/svm/svm.c | 11 ++- > arch/x86/kvm/vmx/pmu_intel.c | 111 +++++++------------------ > arch/x86/kvm/x86.c | 14 +++- > 10 files changed, 228 insertions(+), 118 deletions(-) >
On Fri, Nov 11, 2022, Like Xu wrote: > Starting with Zen4, core PMU on AMD platforms such as Genoa and > Ryzen-7000 will support PerfMonV2, and it is also compatible with > legacy PERFCTR_CORE behavior and msr addresses. > > If you don't have access to the hardware specification, the commits > d6d0c7f681fd..7685665c390d for host perf can also bring a quick > overview. Its main change is the addition of three msr's equivalent > to Intel V2, namely global_ctrl, global_status, global_status_clear. > > It is worth noting that this feature is very attractive for reducing the > overhead of PMU virtualization, since multiple msr accesses to multiple > counters will be replaced by a single access to the global register, > plus more accuracy gain when multiple guest counters are used. Some minor nits, though I haven't looked at the meat of the series yet. I'll give this a thorough review early next week (unless I'm extra ambitious tomorrow).
Starting with Zen4, core PMU on AMD platforms such as Genoa and Ryzen-7000 will support PerfMonV2, and it is also compatible with legacy PERFCTR_CORE behavior and msr addresses. If you don't have access to the hardware specification, the commits d6d0c7f681fd..7685665c390d for host perf can also bring a quick overview. Its main change is the addition of three msr's equivalent to Intel V2, namely global_ctrl, global_status, global_status_clear. It is worth noting that this feature is very attractive for reducing the overhead of PMU virtualization, since multiple msr accesses to multiple counters will be replaced by a single access to the global register, plus more accuracy gain when multiple guest counters are used. All related testcases are passed on a Genoa box. Please feel free to run more tests, add more or share comments. Previous: https://lore.kernel.org/kvm/20220919093453.71737-1-likexu@tencent.com/ V2 -> V3 Changelog: - Renme pmc_is_enabled(); (Jim) - Move the reprogram_counters() changes as a separate patch; (Jim) - Refactoring to align with other set_msr() helper; (Sean) - Fix the issue if userspace wants to expose v1 for whatever reason; (Sean) - Add the feature flag X86_FEATURE_AMD_PMU_V2; (Sean) - Check enable_pmu for intel 0xa as well; (Sean) - Limit AMD pmu's KVM support to version 2 as well; - Other nit changes around C code taste; (Sean) Like Xu (7): KVM: x86/pmu: Rename pmc_is_enabled() to pmc_is_globally_enabled() KVM: x86/pmu: Rewrite reprogram_counters() to improve performance KVM: x86/pmu: Make part of the Intel v2 PMU MSRs handling x86 generic KVM: x86/cpuid: Add X86_FEATURE_AMD_PMU_V2 as a KVM-only leaf entry KVM: x86/svm/pmu: Add AMD PerfMonV2 support KVM: x86/cpuid: Add AMD CPUID ExtPerfMonAndDbg leaf 0x80000022 KVM: x86/cpuid: Use fast return for cpuid "0xa" leaf when !enable_pmu Sean Christopherson (1): KVM: VMX: Refactor intel_pmu_set_msr() to align with other set_msr() helpers arch/x86/include/asm/kvm-x86-pmu-ops.h | 1 - arch/x86/include/asm/kvm_host.h | 1 + arch/x86/kvm/cpuid.c | 32 ++++++- arch/x86/kvm/pmu.c | 65 +++++++++++++-- arch/x86/kvm/pmu.h | 28 ++++++- arch/x86/kvm/reverse_cpuid.h | 10 +++ arch/x86/kvm/svm/pmu.c | 73 +++++++++++----- arch/x86/kvm/svm/svm.c | 11 ++- arch/x86/kvm/vmx/pmu_intel.c | 111 +++++++------------------ arch/x86/kvm/x86.c | 14 +++- 10 files changed, 228 insertions(+), 118 deletions(-)