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X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 05 Apr 2023 18:02:05.4296 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 32c0a2c3-803f-48f9-5185-08db35ffddb6 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.233];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: DM6NAM11FT049.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BL3PR12MB6644 Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org From: Ankit Agrawal NVIDIA's upcoming Grace Hopper Superchip provides a PCI-like device for the on-chip GPU that is the logical OS representation of the internal propritary cache coherent interconnect. This representation has a number of limitations compared to a real PCI device, in particular, it does not model the coherent GPU memory aperture as a PCI config space BAR, and PCI doesn't know anything about cacheable memory types. Provide a VFIO PCI variant driver that adapts the unique PCI representation into a more standard PCI representation facing userspace. The GPU memory aperture is obtained from ACPI, according to the FW specification, and exported to userspace as the VFIO_REGION that covers the first PCI BAR. qemu will naturally generate a PCI device in the VM where the cacheable aperture is reported in BAR1. Since this memory region is actually cache coherent with the CPU, the VFIO variant driver will mmap it into VMA using a cacheable mapping. As this is the first time an ARM environment has placed cacheable non-struct page backed memory (eg from remap_pfn_range) into a KVM page table, fix a bug in ARM KVM where it does not copy the cacheable memory attributes from non-struct page backed PTEs to ensure the guest also gets a cacheable mapping. Finally, the cacheable memory can participate in memory failure handling. ECC failures on this memory will trigger the normal ARM mechanism to get into memory-failure.c. Since this memory is not backed by struct page create a mechanism to route the memory-failure's physical address to the VMA owner so that a SIGBUS can be generated toward the correct process. This works with the existing KVM/qemu handling for memory failure reporting toward a guest. This goes along with a qemu series to provides the necessary implementation of the Grace Hopper Superchip firmware specification so that the guest operating system can see the correct ACPI modeling for the coherent GPU device. https://github.com/qemu/qemu/compare/master...ankita-nv:qemu:dev-ankit/cohmem-0330 Applied and tested over v6.3-rc4. Ankit Agrawal (6): kvm: determine memory type from VMA vfio/nvgpu: expose GPU device memory as BAR1 mm: handle poisoning of pfn without struct pages mm: Add poison error check in fixup_user_fault() for mapped PFN mm: Change ghes code to allow poison of non-struct PFN vfio/nvgpu: register device memory for poison handling MAINTAINERS | 6 + arch/arm64/include/asm/kvm_pgtable.h | 8 +- arch/arm64/include/asm/memory.h | 6 +- arch/arm64/kvm/hyp/pgtable.c | 16 +- arch/arm64/kvm/mmu.c | 27 +- drivers/acpi/apei/ghes.c | 12 +- drivers/vfio/pci/Kconfig | 2 + drivers/vfio/pci/Makefile | 2 + drivers/vfio/pci/nvgpu/Kconfig | 10 + drivers/vfio/pci/nvgpu/Makefile | 3 + drivers/vfio/pci/nvgpu/main.c | 359 +++++++++++++++++++++++++++ include/linux/memory-failure.h | 22 ++ include/linux/mm.h | 1 + include/ras/ras_event.h | 1 + mm/gup.c | 2 +- mm/memory-failure.c | 148 +++++++++-- virt/kvm/kvm_main.c | 6 + 17 files changed, 586 insertions(+), 45 deletions(-) create mode 100644 drivers/vfio/pci/nvgpu/Kconfig create mode 100644 drivers/vfio/pci/nvgpu/Makefile create mode 100644 drivers/vfio/pci/nvgpu/main.c create mode 100644 include/linux/memory-failure.h