From patchwork Tue Aug 1 06:31:23 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Baolu Lu X-Patchwork-Id: 13335826 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id D6A28C001E0 for ; Tue, 1 Aug 2023 06:34:28 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231635AbjHAGe2 (ORCPT ); Tue, 1 Aug 2023 02:34:28 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:47170 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231713AbjHAGeV (ORCPT ); Tue, 1 Aug 2023 02:34:21 -0400 Received: from mgamail.intel.com (unknown [134.134.136.65]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 0B1712708; Mon, 31 Jul 2023 23:34:01 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1690871642; x=1722407642; h=from:to:cc:subject:date:message-id:mime-version: content-transfer-encoding; bh=38X/UQN2S8KMhUmc07Z43oFl0p6G/FE1mEl9dZQsBt4=; b=UD/pRQUvZ9z1C2ODw2rxCzoiBm7gA5Y2o/dT9rOfPUsSiAt4T3bQX2T5 lYJbitr75AtEHsYaR0PK8pZ3oIcH0oeSSkcv+XZRSnPKig/YRB+tUjqKS yWLfqWb/umyl8vOzlB0hyh4QTinPTrXSj1lLCDO8nRGvLPAEbUAktmZ/H qjnV2xY+tEHHwaKg8UAzHLisSr0Q9ebInlOu+R0GmQbLPnA0qwUSq84tg 6Nx0FKkPQhfv6JFras0OSkruRS1ASf+5OKnHPX0hUZGGWX3D75SULCCSh k5evLaDttFvby75alPVLpK1wdpEMtJteCmVba3gb064XjdY2+hEdLEume A==; X-IronPort-AV: E=McAfee;i="6600,9927,10788"; a="372839955" X-IronPort-AV: E=Sophos;i="6.01,246,1684825200"; d="scan'208";a="372839955" Received: from fmsmga004.fm.intel.com ([10.253.24.48]) by orsmga103.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 31 Jul 2023 23:33:37 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10788"; a="798537908" X-IronPort-AV: E=Sophos;i="6.01,246,1684825200"; d="scan'208";a="798537908" Received: from allen-box.sh.intel.com ([10.239.159.127]) by fmsmga004.fm.intel.com with ESMTP; 31 Jul 2023 23:33:34 -0700 From: Lu Baolu To: Joerg Roedel , Will Deacon , Robin Murphy , Jason Gunthorpe , Kevin Tian , Jean-Philippe Brucker , Nicolin Chen Cc: Yi Liu , Jacob Pan , iommu@lists.linux.dev, kvm@vger.kernel.org, linux-kernel@vger.kernel.org, Lu Baolu Subject: [PATCH 0/2] iommu: Make pasid array per device Date: Tue, 1 Aug 2023 14:31:23 +0800 Message-Id: <20230801063125.34995-1-baolu.lu@linux.intel.com> X-Mailer: git-send-email 2.34.1 MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org The PCI PASID enabling interface guarantees that the address space used by each PASID is unique. This is achieved by checking that the PCI ACS path is enabled for the device. If the path is not enabled, then the PASID feature cannot be used. if (!pci_acs_path_enabled(pdev, NULL, PCI_ACS_RR | PCI_ACS_UF)) return -EINVAL; The PASID array is not an attribute of the IOMMU group. It is more natural to store the PASID array in the per-device IOMMU data. This makes the code clearer and easier to understand. No functional changes are intended. Please help review and suggest. Lu Baolu (2): iommu: Consolidate pasid dma ownership check iommu: Move pasid array from group to device include/linux/iommu.h | 2 + drivers/iommu/iommu.c | 105 +++++++++++++++++------------------------- 2 files changed, 43 insertions(+), 64 deletions(-)