[v2,0/9] SVM guest shadow stack support

Message

John Allen Feb. 26, 2024, 9:32 p.m. UTC

AMD Zen3 and newer processors support shadow stack, a feature designed
to protect against ROP (return-oriented programming) attacks in which an
attacker manipulates return addresses on the call stack in order to
execute arbitrary code. To prevent this, shadow stacks can be allocated
that are only used by control transfer and return instructions. When a
CALL instruction is issued, it writes the return address to both the
program stack and the shadow stack. When the subsequent RET instruction
is issued, it pops the return address from both stacks and compares
them. If the addresses don't match, a control-protection exception is
raised.

Shadow stack and a related feature, Indirect Branch Tracking (IBT), are
collectively referred to as Control-flow Enforcement Technology (CET).
However, current AMD processors only support shadow stack and not IBT.

This series adds support for shadow stack in SVM guests and builds upon
the support added in the CET guest support patch series [1]. Additional
patches are required to support shadow stack enabled guests in qemu [2].

[1]: CET guest support patches (v10)
https://lore.kernel.org/all/[e-mail]/

[2]: CET qemu patches
https://lore.kernel.org/all/[e-mail]/

[3]: Initial SVM support series
https://lore.kernel.org/all/[e-mail]/

---

RFC v2:
  - Rebased on v3 of the Intel CET virtualization series, dropping the
    patch that moved cet_is_msr_accessible to common code as that has
    been pulled into the Intel series.
  - Minor change removing curly brackets around if statement introduced
    in patch 6/6.
RFC v3:
  - Rebased on v5 of the Intel CET virtualization series.
  - Add patch changing the name of vmplX_ssp SEV-ES save area fields to
    plX_ssp.
  - Merge this series intended for KVM with the separate guest kernel
    patch (now patch 7/8).
  - Update MSR passthrough code to conditionally pass through shadow
    stack MSRS based on both host and guest support.
  - Don't save PL0_SSP, PL1_SSP, and PL2_SSP MSRs on SEV-ES VMRUN as
    these are currently unused.
v1:
  - Remove RFC tag from series
  - Rebase on v6 of the Intel CET virtualization series
  - Use KVM-governed feature to track SHSTK for SVM
v2:
  - Add new patch renaming boot_*msr to raw_*msr. Utilize raw_rdmsr when
    reading XSS on SEV-ES cpuid instructions.
  - Omit unnecessary patch for saving shadow stack msrs on SEV-ES VMRUN
  - Omit passing through of XSS for SEV-ES as support has already been
    properly implemented in a26b7cd22546 ("KVM: SEV: Do not intercept
    accesses to MSR_IA32_XSS for SEV-ES guests") 

John Allen (9):
  x86/boot: Move boot_*msr helpers to asm/shared/msr.h
  KVM: x86: SVM: Emulate reads and writes to shadow stack MSRs
  KVM: x86: SVM: Update dump_vmcb with shadow stack save area additions
  KVM: x86: SVM: Pass through shadow stack MSRs
  KVM: SVM: Rename vmplX_ssp -> plX_ssp
  KVM: SVM: Add MSR_IA32_XSS to the GHCB for hypervisor kernel
  x86/sev-es: Include XSS value in GHCB CPUID request
  KVM: SVM: Use KVM-governed features to track SHSTK
  KVM: SVM: Add CET features to supported_xss

 arch/x86/boot/compressed/sev.c    | 10 +++---
 arch/x86/boot/cpucheck.c          | 16 +++++-----
 arch/x86/boot/msr.h               | 26 ---------------
 arch/x86/include/asm/shared/msr.h | 15 +++++++++
 arch/x86/include/asm/svm.h        |  9 +++---
 arch/x86/kernel/sev-shared.c      |  7 ++++
 arch/x86/kvm/svm/sev.c            |  9 ++++--
 arch/x86/kvm/svm/svm.c            | 53 +++++++++++++++++++++++++++++++
 arch/x86/kvm/svm/svm.h            |  3 +-
 9 files changed, 102 insertions(+), 46 deletions(-)
 delete mode 100644 arch/x86/boot/msr.h