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([2a01:e0a:999:a3a0:46f0:3724:aa77:c1f8]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-4200e518984sm240669275e9.23.2024.05.17.06.40.09 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 17 May 2024 06:40:10 -0700 (PDT) From: =?utf-8?b?Q2zDqW1lbnQgTMOpZ2Vy?= To: kvm@vger.kernel.org, kvm-riscv@lists.infradead.org Cc: =?utf-8?b?Q2zDqW1lbnQgTMOpZ2Vy?= , Andrew Jones , Anup Patel , Atish Patra Subject: [kvm-unit-tests PATCH v1 0/4] riscv: add SBI SSE extension tests Date: Fri, 17 May 2024 15:40:01 +0200 Message-ID: <20240517134007.928539-1-cleger@rivosinc.com> X-Mailer: git-send-email 2.43.0 Precedence: bulk X-Mailing-List: kvm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 This series adds an individual test for SBI SSE extension as well as needed infrastructure for SSE support. Clément Léger (4): riscv: move REG_L/REG_W in a dedicated asm.h file riscv: add SBI SSE extension definitions riscv: add SSE assembly entry handling riscv: add SBI SSE extension tests riscv/Makefile | 2 + lib/riscv/asm/asm.h | 19 + lib/riscv/asm/csr.h | 2 + lib/riscv/asm/sbi.h | 76 ++++ lib/riscv/asm/sse.h | 16 + lib/riscv/sse_entry.S | 100 ++++ lib/riscv/asm-offsets.c | 9 + riscv/cstart.S | 14 +- riscv/sbi_sse.c | 983 ++++++++++++++++++++++++++++++++++++++++ riscv/unittests.cfg | 4 + 10 files changed, 1212 insertions(+), 13 deletions(-) create mode 100644 lib/riscv/asm/asm.h create mode 100644 lib/riscv/asm/sse.h create mode 100644 lib/riscv/sse_entry.S create mode 100644 riscv/sbi_sse.c