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([202.166.44.78]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-2c4a75ee5a5sm13529305a91.17.2024.06.18.10.32.13 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 18 Jun 2024 10:32:15 -0700 (PDT) From: James Raphael Tiovalen To: kvm@vger.kernel.org, kvm-riscv@lists.infradead.org Cc: andrew.jones@linux.dev, atishp@rivosinc.com, cade.richard@berkeley.edu, James Raphael Tiovalen Subject: [kvm-unit-tests PATCH 0/4] riscv: sbi: Add support to test timer extension Date: Wed, 19 Jun 2024 01:30:49 +0800 Message-ID: <20240618173053.364776-1-jamestiotio@gmail.com> X-Mailer: git-send-email 2.43.0 Precedence: bulk X-Mailing-List: kvm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 This patch series adds support for testing the timer extension as defined in the RISC-V SBI specification. The first 3 patches add infrastructural support for handling interrupts, while the last patch adds the actual test for the timer extension. James Raphael Tiovalen (4): riscv: Extend exception handling support for interrupts riscv: Update exception cause list riscv: Add methods to toggle interrupt enable bits riscv: sbi: Add test for timer extension riscv/Makefile | 1 + lib/riscv/asm/csr.h | 30 +++++++++++--- lib/riscv/asm/interrupt.h | 12 ++++++ lib/riscv/asm/processor.h | 15 ++++++- lib/riscv/asm/sbi.h | 5 +++ lib/riscv/interrupt.c | 39 ++++++++++++++++++ lib/riscv/processor.c | 27 ++++++++++-- riscv/sbi.c | 87 +++++++++++++++++++++++++++++++++++++++ 8 files changed, 205 insertions(+), 11 deletions(-) create mode 100644 lib/riscv/asm/interrupt.h create mode 100644 lib/riscv/interrupt.c --- 2.43.0