Message ID | 20240827152517.3909653-1-maz@kernel.org (mailing list archive) |
---|---|
Headers | show |
Series | KVM: arm64: Handle the lack of GICv3 exposed to a guest | expand |
On Tue, Aug 27, 2024 at 04:25:06PM +0100, Marc Zyngier wrote: > It recently appeared that, when running on a GICv3-equipped platform > (which is what non-ancient arm64 HW has), *not* configuring a GICv3 > for the guest could result in less than desirable outcomes. > > We have multiple issues to fix: > > - for registers that *always* trap (the SGI registers) or that *may* > trap (the SRE register), we need to check whether a GICv3 has been > instantiated before acting upon the trap. > > - for registers that only conditionally trap, we must actively trap > them even in the absence of a GICv3 being instantiated, and handle > those traps accordingly. > > - finally, ID registers must reflect the absence of a GICv3, so that > we are consistent. > > This series goes through all these requirements. The main complexity > here is to apply a GICv3 configuration on the host in the absence of a > GICv3 in the guest. This is pretty hackish, but I don't have a much > better solution so far. LGTM, thanks for respinning. Reviewed-by: Oliver Upton <oliver.upton@linux.dev>
On Tue, 27 Aug 2024 16:25:06 +0100, Marc Zyngier wrote: > It recently appeared that, when running on a GICv3-equipped platform > (which is what non-ancient arm64 HW has), *not* configuring a GICv3 > for the guest could result in less than desirable outcomes. > > We have multiple issues to fix: > > - for registers that *always* trap (the SGI registers) or that *may* > trap (the SRE register), we need to check whether a GICv3 has been > instantiated before acting upon the trap. > > [...] Applied to next, thanks! [01/11] KVM: arm64: Move GICv3 trap configuration to kvm_calculate_traps() commit: d2137ba8d8fe56cd2470c82b98e494cbcababd76 [02/11] KVM: arm64: Force SRE traps when SRE access is not enabled commit: 5739a961b542530626cb3afb721efa688b290cce [03/11] KVM: arm64: Force GICv3 trap activation when no irqchip is configured on VHE commit: 8d917e0a8651377321c06513f42e2ab9a86161f4 [04/11] KVM: arm64: Add helper for last ditch idreg adjustments commit: 795a0bbaeee2aa993338166bc063fe3c89373d2a [05/11] KVM: arm64: Zero ID_AA64PFR0_EL1.GIC when no GICv3 is presented to the guest commit: 5cb57a1aff7551bcb3b800d33141b06ef0ac178b [06/11] KVM: arm64: Add ICH_HCR_EL2 to the vcpu state commit: 9f5deace58da737d67ec9c2d23534a475be68481 [07/11] KVM: arm64: Add trap routing information for ICH_HCR_EL2 commit: 15a1ba8d049855c5ae454c84e6dd2d7657bacbe8 [08/11] KVM: arm64: Honor guest requested traps in GICv3 emulation commit: 59af011d001b836aa52a3dbb5c54daf6fffb511e [09/11] KVM: arm64: Make most GICv3 accesses UNDEF if they trap commit: 4a999a1d7ae52592723a9a219aaa7a3406d66dd6 [10/11] KVM: arm64: Unify UNDEF injection helpers commit: cd08d3216fc4e684f05fe4cf696a275a975f6499 [11/11] KVM: arm64: Add selftest checking how the absence of GICv3 is handled commit: de2e75209303b98d3169a249a1bc847be9657d9b Cheers, M.