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([2a01:e0a:e17:9700:16d2:7456:6634:9626]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-2ead04d2b9dsm5153370a91.33.2024.11.22.06.05.09 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 22 Nov 2024 06:05:13 -0800 (PST) From: =?utf-8?b?Q2zDqW1lbnQgTMOpZ2Vy?= To: kvm@vger.kernel.org, kvm-riscv@lists.infradead.org Cc: =?utf-8?b?Q2zDqW1lbnQgTMOpZ2Vy?= , Andrew Jones , Anup Patel , Atish Patra Subject: [kvm-unit-tests PATCH v2 0/3] riscv: add SBI SSE extension tests Date: Fri, 22 Nov 2024 15:04:54 +0100 Message-ID: <20241122140459.566306-1-cleger@rivosinc.com> X-Mailer: git-send-email 2.45.2 Precedence: bulk X-Mailing-List: kvm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 This series adds an individual test for SBI SSE extension as well as needed infrastructure for SSE support. --- V2: - Rebased on origin/master and integrate it into sbi.c tests Clément Léger (3): riscv: lib: Add SBI SSE extension definitions riscv: lib: Add SSE assembly entry handling riscv: sbi: Add SSE extension tests riscv/Makefile | 2 + lib/riscv/asm/csr.h | 2 + lib/riscv/asm/sbi.h | 76 ++++ lib/riscv/asm/sse.h | 16 + lib/riscv/sse-entry.S | 100 ++++ lib/riscv/asm-offsets.c | 9 + riscv/sbi-tests.h | 4 + riscv/sbi-sse.c | 981 ++++++++++++++++++++++++++++++++++++++++ riscv/sbi.c | 1 + riscv/unittests.cfg | 4 + 10 files changed, 1195 insertions(+) create mode 100644 lib/riscv/asm/sse.h create mode 100644 lib/riscv/sse-entry.S create mode 100644 riscv/sbi-sse.c