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client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; pr=C Received: from SATLEXMB04.amd.com (165.204.84.17) by CH2PEPF00000146.mail.protection.outlook.com (10.167.244.103) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.8314.11 via Frontend Transport; Thu, 2 Jan 2025 18:50:34 +0000 Received: from MKM-L10-YUNXIA9.amd.com (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.39; Thu, 2 Jan 2025 12:50:33 -0600 From: Yunxiang Li To: , CC: , , , , Yunxiang Li Subject: [PATCH v2 0/2] Use setup ROM as fallback for ROM bar Date: Thu, 2 Jan 2025 13:50:11 -0500 Message-ID: <20250102185013.15082-1-Yunxiang.Li@amd.com> X-Mailer: git-send-email 2.34.1 Precedence: bulk X-Mailing-List: kvm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CH2PEPF00000146:EE_|DM4PR12MB6352:EE_ X-MS-Office365-Filtering-Correlation-Id: 17a79f25-958b-4679-8df7-08dd2b5e5758 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|36860700013|82310400026|1800799024|376014; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 02 Jan 2025 18:50:34.8038 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 17a79f25-958b-4679-8df7-08dd2b5e5758 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CH2PEPF00000146.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM4PR12MB6352 On some servers the upstream bridge does not have enough address window for the ROM bar, currently this will result in the vdev not having a ROM bar and this causes issues if ROM content is needed by the guest driver. On x86 the device's ROM may be passed via setup data to pdev->rom, so it can be used as a fallback. However, it can't be exposed transparently as a PCI resource like the shadow ROM, because it is not aligned to power of two boundaries. So special handling need to be added in vfio to make use of this data just like in the GPU drivers. Yunxiang Li (2): vfio/pci: Remove shadow ROM specific code paths vfio/pci: Expose setup ROM at ROM bar when needed drivers/vfio/pci/vfio_pci_config.c | 8 +++--- drivers/vfio/pci/vfio_pci_core.c | 40 ++++++++++++++---------------- drivers/vfio/pci/vfio_pci_rdwr.c | 25 ++++++++++++------- 3 files changed, 38 insertions(+), 35 deletions(-)