| Message ID | 20250117234204.2600624-1-seanjc@google.com (mailing list archive) |
|---|---|
| Headers | show |
| Series | KVM: selftests: Fix PMC checks in PMU counters test | expand |
On Sat, Jan 18, 2025 at 12:42 AM Sean Christopherson <seanjc@google.com> wrote: > > Fix a flaw in the Intel PMU counters test where it asserts that an event is > counting correctly without actually knowing what the event counts given the > underlying hardware. > > The bug manifests as failures with the Top-Down Slots architectural event > when running CPUs that doesn't actually support that arch event (pre-ICX). > The arch event encoding still counts _something_, just not Top-Down Slots > (I haven't bothered to look up what it was counting). The passed by sheer > dumb luck until an unrelated change caused the count of the unknown event > to drop. Queued for 6.14-rc1, thanks. Paolo
Fix a flaw in the Intel PMU counters test where it asserts that an event is counting correctly without actually knowing what the event counts given the underlying hardware. The bug manifests as failures with the Top-Down Slots architectural event when running CPUs that doesn't actually support that arch event (pre-ICX). The arch event encoding still counts _something_, just not Top-Down Slots (I haven't bothered to look up what it was counting). The passed by sheer dumb luck until an unrelated change caused the count of the unknown event to drop. All credit to Dapeng for hunting down the problem. Sean Christopherson (5): KVM: selftests: Make Intel arch events globally available in PMU counters test KVM: selftests: Only validate counts for hardware-supported arch events KVM: selftests: Remove dead code in Intel PMU counters test KVM: selftests: Drop the "feature event" param from guest test helpers KVM: selftests: Print out the actual Top-Down Slots count on failure .../selftests/kvm/x86/pmu_counters_test.c | 143 ++++++++++-------- 1 file changed, 83 insertions(+), 60 deletions(-) base-commit: eb723766b1030a23c38adf2348b7c3d1409d11f0