mbox series

[v2,0/2] INVD intercept change to skip instruction

Message ID cover.1600972918.git.thomas.lendacky@amd.com (mailing list archive)
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Series INVD intercept change to skip instruction | expand

Message

Tom Lendacky Sept. 24, 2020, 6:41 p.m. UTC
From: Tom Lendacky <thomas.lendacky@amd.com>

This series updates the INVD intercept support for both SVM and VMX to
skip the instruction rather than emulating it, since emulation of this
instruction is just a NOP.

For SVM, it requires creating a dedicated INVD intercept routine that
invokes kvm_skip_emulated_instruction(). The current support uses the
common emulate_on_interception() routine, which does not work for SEV
guests, and so a Fixes: tag is added.

For VMX, which already has a dedicated INVD intercept routine, it changes
kvm_emulate_instruction() into a call to kvm_skip_emulated_instruction().

Tom Lendacky (2):
  KVM: SVM: Add a dedicated INVD intercept routine
  KVM: VMX: Do not perform emulation for INVD intercept

 arch/x86/kvm/svm/svm.c | 8 +++++++-
 arch/x86/kvm/vmx/vmx.c | 3 ++-
 2 files changed, 9 insertions(+), 2 deletions(-)

Comments

Jim Mattson Sept. 24, 2020, 9:20 p.m. UTC | #1
On Thu, Sep 24, 2020 at 11:42 AM Tom Lendacky <thomas.lendacky@amd.com> wrote:
>
> From: Tom Lendacky <thomas.lendacky@amd.com>
>
> This series updates the INVD intercept support for both SVM and VMX to
> skip the instruction rather than emulating it, since emulation of this
> instruction is just a NOP.

Isn't INVD a serializing instruction, whereas NOP isn't? IIRC, Intel
doesn't architect VM-entry or VM-exit as serializing, though they
probably are in practice. I'm not sure what AMD's stance on this is.
Paolo Bonzini Sept. 25, 2020, 5:31 p.m. UTC | #2
On 24/09/20 23:20, Jim Mattson wrote:
> On Thu, Sep 24, 2020 at 11:42 AM Tom Lendacky <thomas.lendacky@amd.com> wrote:
>>
>> From: Tom Lendacky <thomas.lendacky@amd.com>
>>
>> This series updates the INVD intercept support for both SVM and VMX to
>> skip the instruction rather than emulating it, since emulation of this
>> instruction is just a NOP.
> 
> Isn't INVD a serializing instruction, whereas NOP isn't? IIRC, Intel
> doesn't architect VM-entry or VM-exit as serializing, though they
> probably are in practice. I'm not sure what AMD's stance on this is.

Of course that isn't changed by this patch, though.

Queuing both, but a clarification would be useful.  The same applies
even to CPUID.

Paolo