Show patches with: Series = Add RISC-V vector cryptographic instruction set support       |    State = Action Required       |   19 patches
Patch Series A/R/T S/W/F Date Submitter Delegate State
[v3,19/19] target/riscv: Expose Zvk* and Zvb[b,c] cpu properties Add RISC-V vector cryptographic instruction set support - 1 - --- 2023-04-28 Lawrence Hunter New
[v3,18/19] target/riscv: Add Zvksed ISA extension support Add RISC-V vector cryptographic instruction set support - 1 - --- 2023-04-28 Lawrence Hunter New
[v3,17/19] crypto: Add SM4 constant parameter CK Add RISC-V vector cryptographic instruction set support - 1 - --- 2023-04-28 Lawrence Hunter New
[v3,16/19] crypto: Create sm4_subword Add RISC-V vector cryptographic instruction set support - 2 - --- 2023-04-28 Lawrence Hunter New
[v3,15/19] target/riscv: Add Zvkg ISA extension support Add RISC-V vector cryptographic instruction set support - - - --- 2023-04-28 Lawrence Hunter New
[v3,14/19] target/riscv: Add Zvksh ISA extension support Add RISC-V vector cryptographic instruction set support - - - --- 2023-04-28 Lawrence Hunter New
[v3,13/19] target/riscv: Add Zvknh ISA extension support Add RISC-V vector cryptographic instruction set support - - - --- 2023-04-28 Lawrence Hunter New
[v3,12/19] target/riscv: Add Zvkned ISA extension support Add RISC-V vector cryptographic instruction set support - - - --- 2023-04-28 Lawrence Hunter New
[v3,11/19] target/riscv: Add Zvbb ISA extension support Add RISC-V vector cryptographic instruction set support - - - --- 2023-04-28 Lawrence Hunter New
[v3,10/19] qemu/host-utils.h: Add clz and ctz functions for lower-bit integers Add RISC-V vector cryptographic instruction set support - 1 - --- 2023-04-28 Lawrence Hunter New
[v3,09/19] tcg: Add andcs and rotrs tcg gvec ops Add RISC-V vector cryptographic instruction set support - - - --- 2023-04-28 Lawrence Hunter New
[v3,08/19] qemu/bitops.h: Limit rotate amounts Add RISC-V vector cryptographic instruction set support - 1 - --- 2023-04-28 Lawrence Hunter New
[v3,07/19] target/riscv: Refactor some of the generic vector functionality Add RISC-V vector cryptographic instruction set support - 1 - --- 2023-04-28 Lawrence Hunter New
[v3,06/19] target/riscv: Refactor translation of vector-widening instruction Add RISC-V vector cryptographic instruction set support - 2 - --- 2023-04-28 Lawrence Hunter New
[v3,05/19] target/riscv: Move vector translation checks Add RISC-V vector cryptographic instruction set support - 2 - --- 2023-04-28 Lawrence Hunter New
[v3,04/19] target/riscv: Add Zvbc ISA extension support Add RISC-V vector cryptographic instruction set support - - - --- 2023-04-28 Lawrence Hunter New
[v3,03/19] target/riscv: Remove redundant "cpu_vl == 0" checks Add RISC-V vector cryptographic instruction set support - 1 - --- 2023-04-28 Lawrence Hunter New
[v3,02/19] target/riscv: Refactor vector-vector translation macro Add RISC-V vector cryptographic instruction set support - 3 - --- 2023-04-28 Lawrence Hunter New
[v3,01/19] target/riscv: Refactor some of the generic vector functionality Add RISC-V vector cryptographic instruction set support - 1 - --- 2023-04-28 Lawrence Hunter New