From patchwork Fri Jan 9 21:27:35 2009 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andre Przywara X-Patchwork-Id: 1638 Received: from vger.kernel.org (vger.kernel.org [209.132.176.167]) by demeter.kernel.org (8.14.2/8.14.2) with ESMTP id n09LOJC9017282 for ; Fri, 9 Jan 2009 13:24:19 -0800 Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753306AbZAIV1i (ORCPT ); Fri, 9 Jan 2009 16:27:38 -0500 Received: (majordomo@vger.kernel.org) by vger.kernel.org id S1755354AbZAIV1i (ORCPT ); Fri, 9 Jan 2009 16:27:38 -0500 Received: from outbound-dub.frontbridge.com ([213.199.154.16]:1914 "EHLO IE1EHSOBE004.bigfish.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753306AbZAIV1h (ORCPT ); Fri, 9 Jan 2009 16:27:37 -0500 Received: from mail56-dub-R.bigfish.com (10.5.252.3) by IE1EHSOBE004.bigfish.com (10.5.252.24) with Microsoft SMTP Server id 8.1.291.1; Fri, 9 Jan 2009 21:27:35 +0000 Received: from mail56-dub (localhost.localdomain [127.0.0.1]) by mail56-dub-R.bigfish.com (Postfix) with ESMTP id C7CE217880FD; Fri, 9 Jan 2009 21:27:34 +0000 (UTC) X-BigFish: VPS3(zzzzzzz32i43j62h) X-Spam-TCS-SCL: 1:0 Received: by mail56-dub (MessageSwitch) id 1231536453538886_22987; Fri, 9 Jan 2009 21:27:33 +0000 (UCT) Received: from ausb3extmailp01.amd.com (unknown [163.181.251.8]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) by mail56-dub.bigfish.com (Postfix) with ESMTP id D3655168006D; Fri, 9 Jan 2009 21:27:32 +0000 (UTC) Received: from ausb3twp02.amd.com ([163.181.250.38]) by ausb3extmailp01.amd.com (Switch-3.2.7/Switch-3.2.7) with ESMTP id n09LRP66013042; Fri, 9 Jan 2009 15:27:28 -0600 X-WSS-ID: 0KD83LF-02-NDU-01 Received: from sausexbh2.amd.com (SAUSEXBH2.amd.com [163.181.22.102]) by ausb3twp02.amd.com (Tumbleweed MailGate 3.5.1) with ESMTP id 2F58516A0628; Fri, 9 Jan 2009 15:27:14 -0600 (CST) Received: from sausexmb1.amd.com ([163.181.3.156]) by sausexbh2.amd.com with Microsoft SMTPSVC(6.0.3790.3959); Fri, 9 Jan 2009 15:27:26 -0600 Received: from SDRSEXMB1.amd.com ([172.20.3.116]) by sausexmb1.amd.com with Microsoft SMTPSVC(6.0.3790.3959); Fri, 9 Jan 2009 15:27:25 -0600 Received: from localhost.localdomain ([165.204.85.48]) by SDRSEXMB1.amd.com with Microsoft SMTPSVC(6.0.3790.3959); Fri, 9 Jan 2009 22:27:07 +0100 From: Andre Przywara To: avi@redhat.com CC: amit.shah@redhat.com, kvm@vger.kernel.org, Andre Przywara Subject: [PATCH] set accessed bit for VMCB segment selectors Date: Fri, 9 Jan 2009 22:27:35 +0100 Message-ID: <12315364554190-git-send-email-andre.przywara@amd.com> X-Mailer: git-send-email 1.5.2.2 In-Reply-To: <49678FF9.2040404@redhat.com> References: <49678FF9.2040404@redhat.com> X-OriginalArrivalTime: 09 Jan 2009 21:27:07.0005 (UTC) FILETIME=[05D70AD0:01C972A1] MIME-Version: 1.0 Sender: kvm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org In the segment descriptor _cache_ the accessed bit is always set (although it can be cleared in the descriptor itself). Since Intel checks for this condition on a VMENTRY, set this bit in the AMD path to enable cross vendor migration. Signed-off-by: Andre Przywara Acked-By: Amit Shah --- arch/x86/kvm/svm.c | 22 +++++++++++++++++++--- 1 files changed, 19 insertions(+), 3 deletions(-) diff --git a/arch/x86/kvm/svm.c b/arch/x86/kvm/svm.c index 32dafb7..ffaba66 100644 --- a/arch/x86/kvm/svm.c +++ b/arch/x86/kvm/svm.c @@ -793,20 +793,36 @@ static void svm_get_segment(struct kvm_vcpu *vcpu, var->db = (s->attrib >> SVM_SELECTOR_DB_SHIFT) & 1; var->g = (s->attrib >> SVM_SELECTOR_G_SHIFT) & 1; + switch (seg) { + case VCPU_SREG_CS: /* * SVM always stores 0 for the 'G' bit in the CS selector in * the VMCB on a VMEXIT. This hurts cross-vendor migration: * Intel's VMENTRY has a check on the 'G' bit. */ - if (seg == VCPU_SREG_CS) var->g = s->limit > 0xfffff; - + break; + case VCPU_SREG_TR: /* * Work around a bug where the busy flag in the tr selector * isn't exposed */ - if (seg == VCPU_SREG_TR) var->type |= 0x2; + break; + case VCPU_SREG_DS: + case VCPU_SREG_ES: + case VCPU_SREG_FS: + case VCPU_SREG_GS: + /* + * The accessed bit must always be set in the segment + * descriptor cache, although it can be cleared in the + * descriptor, the cached bit always remains at 1. Since + * Intel has a check on this, set it here to support + * cross-vendor migration. + */ + if (!var->unusable) var->type |= 0x1; + break; + } var->unusable = !var->present; }