From patchwork Mon Feb 2 15:23:50 2009 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alexander Graf X-Patchwork-Id: 5067 Received: from vger.kernel.org (vger.kernel.org [209.132.176.167]) by demeter.kernel.org (8.14.2/8.14.2) with ESMTP id n12FNvLS028874 for ; Mon, 2 Feb 2009 15:23:58 GMT Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752538AbZBBPX5 (ORCPT ); Mon, 2 Feb 2009 10:23:57 -0500 Received: (majordomo@vger.kernel.org) by vger.kernel.org id S1752584AbZBBPX4 (ORCPT ); Mon, 2 Feb 2009 10:23:56 -0500 Received: from cantor2.suse.de ([195.135.220.15]:45656 "EHLO mx2.suse.de" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752600AbZBBPXy (ORCPT ); Mon, 2 Feb 2009 10:23:54 -0500 Received: from Relay1.suse.de (relay-ext.suse.de [195.135.221.8]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) by mx2.suse.de (Postfix) with ESMTP id 40CC84793A; Mon, 2 Feb 2009 16:23:53 +0100 (CET) From: Alexander Graf To: kvm@vger.kernel.org Cc: avi@redhat.com, Joerg Roedel Subject: [PATCH 1/2] Add EFER descriptions for FFXSR Date: Mon, 2 Feb 2009 16:23:50 +0100 Message-Id: <1233588231-12649-2-git-send-email-agraf@suse.de> X-Mailer: git-send-email 1.6.0.2 In-Reply-To: <1233588231-12649-1-git-send-email-agraf@suse.de> References: <1233588231-12649-1-git-send-email-agraf@suse.de> Sender: kvm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org AMD k10 includes support for the FFXSR feature, which leaves out XMM registers on FXSAVE/FXSAVE when the EFER_FFXSR bit is set in EFER. The CPUID feature bit exists already, but the EFER bit is missing currently, so this patch adds it to the list of known EFER bits. Signed-off-by: Alexander Graf CC: Joerg Roedel --- arch/x86/include/asm/msr-index.h | 2 ++ 1 files changed, 2 insertions(+), 0 deletions(-) diff --git a/arch/x86/include/asm/msr-index.h b/arch/x86/include/asm/msr-index.h index 1890032..42378af 100644 --- a/arch/x86/include/asm/msr-index.h +++ b/arch/x86/include/asm/msr-index.h @@ -19,12 +19,14 @@ #define _EFER_LMA 10 /* Long mode active (read-only) */ #define _EFER_NX 11 /* No execute enable */ #define _EFER_SVME 12 /* Enable virtualization */ +#define _EFER_FFXSR 14 /* Enable Fast FXSAVE/FXRSTOR */ #define EFER_SCE (1<<_EFER_SCE) #define EFER_LME (1<<_EFER_LME) #define EFER_LMA (1<<_EFER_LMA) #define EFER_NX (1<<_EFER_NX) #define EFER_SVME (1<<_EFER_SVME) +#define EFER_FFXSR (1<<_EFER_FFXSR) /* Intel MSRs. Some also available on other CPUs */ #define MSR_IA32_PERFCTR0 0x000000c1