From patchwork Thu Jun 4 21:29:50 2009 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nitin A Kamble X-Patchwork-Id: 28039 Received: from vger.kernel.org (vger.kernel.org [209.132.176.167]) by demeter.kernel.org (8.14.2/8.14.2) with ESMTP id n54LYvNi016822 for ; Thu, 4 Jun 2009 21:34:58 GMT Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1755463AbZFDVbV (ORCPT ); Thu, 4 Jun 2009 17:31:21 -0400 Received: (majordomo@vger.kernel.org) by vger.kernel.org id S1755478AbZFDVbU (ORCPT ); Thu, 4 Jun 2009 17:31:20 -0400 Received: from mga02.intel.com ([134.134.136.20]:20513 "EHLO mga02.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1755463AbZFDVbT (ORCPT ); Thu, 4 Jun 2009 17:31:19 -0400 Received: from orsmga001.jf.intel.com ([10.7.209.18]) by orsmga101.jf.intel.com with ESMTP; 04 Jun 2009 14:23:05 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="4.41,307,1241420400"; d="scan'208";a="521870453" Received: from los-vmm.sc.intel.com ([172.25.110.30]) by orsmga001.jf.intel.com with ESMTP; 04 Jun 2009 14:31:17 -0700 Received: from los-vmm.sc.intel.com (localhost.localdomain [127.0.0.1]) by los-vmm.sc.intel.com (8.14.3/8.14.3) with ESMTP id n54LTphQ008259; Thu, 4 Jun 2009 14:29:51 -0700 Received: (from nitin@localhost) by los-vmm.sc.intel.com (8.14.3/8.14.3/Submit) id n54LTofh008257; Thu, 4 Jun 2009 14:29:50 -0700 X-Authentication-Warning: los-vmm.sc.intel.com: nitin set sender to nitin.a.kamble@intel.com using -f From: Nitin A Kamble To: qemu-devel@nongnu.org Cc: kvm@vger.kernel.org, avi@redhat.com, jan.kiszka@siemens.com, Nitin A Kamble Subject: [PATCH] QEMU KVM: i386: Fix the cpu reset state Date: Thu, 4 Jun 2009 14:29:50 -0700 Message-Id: <1244150990-8234-1-git-send-email-nitin.a.kamble@intel.com> X-Mailer: git-send-email 1.6.0.6 In-Reply-To: References: Sender: kvm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org As per the IA32 processor manual, the accessed bit is set to 1 in the processor state after reset. qemu pc cpu_reset code was missing this accessed bit setting. Signed-off-by: Nitin A Kamble Acked-by: Jan Kiszka --- target-i386/helper.c | 18 ++++++++++++------ 1 files changed, 12 insertions(+), 6 deletions(-) diff --git a/target-i386/helper.c b/target-i386/helper.c index 7fc5366..573fb5b 100644 --- a/target-i386/helper.c +++ b/target-i386/helper.c @@ -493,17 +493,23 @@ void cpu_reset(CPUX86State *env) env->tr.flags = DESC_P_MASK | (11 << DESC_TYPE_SHIFT); cpu_x86_load_seg_cache(env, R_CS, 0xf000, 0xffff0000, 0xffff, - DESC_P_MASK | DESC_S_MASK | DESC_CS_MASK | DESC_R_MASK); + DESC_P_MASK | DESC_S_MASK | DESC_CS_MASK | + DESC_R_MASK | DESC_A_MASK); cpu_x86_load_seg_cache(env, R_DS, 0, 0, 0xffff, - DESC_P_MASK | DESC_S_MASK | DESC_W_MASK); + DESC_P_MASK | DESC_S_MASK | DESC_W_MASK | + DESC_A_MASK); cpu_x86_load_seg_cache(env, R_ES, 0, 0, 0xffff, - DESC_P_MASK | DESC_S_MASK | DESC_W_MASK); + DESC_P_MASK | DESC_S_MASK | DESC_W_MASK | + DESC_A_MASK); cpu_x86_load_seg_cache(env, R_SS, 0, 0, 0xffff, - DESC_P_MASK | DESC_S_MASK | DESC_W_MASK); + DESC_P_MASK | DESC_S_MASK | DESC_W_MASK | + DESC_A_MASK); cpu_x86_load_seg_cache(env, R_FS, 0, 0, 0xffff, - DESC_P_MASK | DESC_S_MASK | DESC_W_MASK); + DESC_P_MASK | DESC_S_MASK | DESC_W_MASK | + DESC_A_MASK); cpu_x86_load_seg_cache(env, R_GS, 0, 0, 0xffff, - DESC_P_MASK | DESC_S_MASK | DESC_W_MASK); + DESC_P_MASK | DESC_S_MASK | DESC_W_MASK | + DESC_A_MASK); env->eip = 0xfff0; env->regs[R_EDX] = env->cpuid_version;